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tangxifan 0053c57954 [Arch] Update architecture file 2020-10-09 18:32:31 -06:00
ARCH [Arch] Update architecture file 2020-10-09 18:32:31 -06:00
SCRIPT [Script] Now use variables to redirect the output directory of Verilog/SDC files 2020-10-09 16:00:41 -06:00
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README.md

skywater-openfpga

FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA