mirror of https://github.com/lnis-uofu/SOFA.git
87 lines
3.8 KiB
Markdown
87 lines
3.8 KiB
Markdown
# SOFA
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[](https://github.com/LNIS-Projects/skywater-openfpga/actions)
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[](https://skywater-openfpga.readthedocs.io/en/latest/?badge=latest)
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## Introduction
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SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK](https://github.com/google/skywater-pdk) and [OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) framework.
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This repository provide the following support for the eFPGA IPs
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- **Architecture description file** : Users can inspect architecture details and try architecture evalution using the [VTR project](https://github.com/verilog-to-routing/vtr-verilog-to-routing) and the [OpenFPGA project](https://github.com/lnis-uofu/OpenFPGA).
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- **Fabrication-ready GDSII layouts**: Users can integrate to their chip designs.
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- **Post-layout Verilog Netlists**: Users can run HDL simulations on the eFPGA IPs to validate their applications
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- **Benchmark suites**: An example benchmarking suite with which users can run quick examples on the eFPGA IPs
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- **Documentation**: Datasheets for each eFPGA IPs downto circuit-level details
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<p>
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<img src="./DOC/source/device/hd_fpga/figures/sofa_hd_layout.png" width="200">
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<img src="./DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png" width="200">
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<img src="./DOC/source/device/hd_fpga/figures/sofa_chd_layout.png" width="200">
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</p>
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## Quick Start
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To run the user flow using SOFA repository you need to have OpenFPGA installed.
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Please visit https://github.com/lnis-uofu/OpenFPGA#compilation for OpenFPGA installaton.
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```bash
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export OPENFPGA_PATH=<path_to_openfpga_root>
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# Clone the SOFA repository
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git clone https://github.com/lnis-uofu/SOFA.git
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# ======== Goto specific design ========
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# FPGA1212_SOFA_CHD_PNR
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# FPGA1212_QLSOFA_HD_PNR
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# FPGA1212_SOFA_HD_PNR
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cd FPGA1212_QLSOFA_HD_PNR
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# ======== Run example OpenFPGA Task ========
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make runOpenFPGA
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# ======== To view the results ========
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cat FPGA1212_QLSOFA_HD_task/latest/task_result.csv
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# ======== To view detailed log ========
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cat codeopen FPGA1212_QLSOFA_HD_task/latest/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/**/openfpgashell.log
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```
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### To bechmark your own design
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Copy your verilog file `FPGA1212_QLSOFA_HD_task/micro_benchmark` directory
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and modify `FPGA1212_QLSOFA_HD_task/config/task_simulation.conf` file.
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Details of different paramters can be found [Configure run_fpga_task](https://openfpga.readthedocs.io/en/latest/manual/openfpga_flow/run_fpga_task/)
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```bash
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cd FPGA1212_QLSOFA_HD_PNR
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vi FPGA1212_QLSOFA_HD_task/config/task_simulation.conf
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```
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---
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## Documentation
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You can find a chip gallery as well as datasheets in the [online documentation](https://skywater-openfpga.readthedocs.io/en/latest/)
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## Directory Organization
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* Keep this folder clean and organized as follows
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- **DOC**: documentation of the project
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- **ARCH**: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists
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- **BENCHMARK**: Benchmarks to be tested on the FPGA fabric
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- **HDL**: Hardware description netlists for the FPGA fabrics
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- **SDC**: design constraints
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- **SCRIPT**: Scripts to setup, run OpenFPGA etc.
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- **TESTBENCH**: Verilog testbenches generated by OpenFPGA
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- **PDK**: Technology files linked from skywater opensource pdk
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- **SNPS\_ICC2**: workspace of Synopsys IC Compiler 2
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Keep a README inside the folder about the ICC2 version and how-to-use.
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- **MSIM**: workspace of verification using Mentor ModelSim
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---
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* Note:
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- Please **ONLY** place folders under this directory.
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README should be the **ONLY** file under this directory
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- Each EDA tool should have **independent** workspace in separated directories
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