mirror of https://github.com/lnis-uofu/SOFA.git
95 lines
3.7 KiB
Makefile
95 lines
3.7 KiB
Makefile
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## = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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## Verification makefile for FPGA1212_RESET_HD_SKY_PNR (Caravel-QLSOFA-HD)
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## = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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SHELL=bash
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PYTHON_EXEC=python3.8
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RERUN = 0
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TB = top
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OPTIONS =
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SIM = modelsim
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TEST_FILE = fpga_reset_hd_sky_pnr
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.SILENT:
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.ONESHELL:
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## Copy all the POSTPnR files from realease directory
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UpdatePostPnRNetlist:
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source ../config.sh
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DESIGN_NAME=$${TOP_MODULE:-$${DESIGN_NAME}}
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echo "Collecting files $${DESIGN_NAME}"
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cp ../pnr/$${DESIGN_NAME}/outputs_icc2/$${DESIGN_NAME}_icv_in_design.pt.v . || \
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cp ../$${DESIGN_NAME}/outputs_icc2/$${DESIGN_NAME}_icv_in_design.pt.v . || :
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## Create symbolic links and run test
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RunPostPnRTest:
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source ../config.sh
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INCLUDE_POSTPNR=$${INCLUDE_POSTPNR:-include_postpnr}
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DESIGN_NAME=$${TOP_MODULE:-$${DESIGN_NAME}}
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VerificationFile=$${TEST_FILE:-${TEST_FILE}}
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# = = = = = = = = = = = = = = Log Information = = = = = = = = = = = =
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echo "DESIGN_NAME = $${DESIGN_NAME}"
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echo "VerificationFile = $${DESIGN_NAME}"
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echo "INCLUDE_FILE = $${INCLUDE_POSTPNR}"
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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echo $${VerificationFile}
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if [ ! -f "./$${VerificationFile}.py" ]; then
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echo "Test file not found $${VerificationFile}.py"
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fi
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echo "Using test file $${VerificationFile}.py"
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Tests=`grep -A 1 "^@cocotb.test" ./$${VerificationFile}.py | grep "def" | sed "s/.*def \(.*\)(.*/\1/g"`
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select RUN_TB in $${Tests}
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do
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echo "Running $${RUN_TB} Test"
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if [[ -d "$${RUN_TB}_run" ]] && [[ -z "$${RERUN}" ]]; then
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echo "Skipping copying source, which will skip the compilations";
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cp *_tests.py ./$${RUN_TB}_run;
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cd $${RUN_TB}_run; break;
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fi
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# = = = = = = = = = = = Prepare Netlist = = = = = = = = = = = = = =
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# = = = = = = = = = = = Copy python test = = = = = = = = = = = = =
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mkdir -p "$${RUN_TB}_run"
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cp $${VerificationFile}.py ./$${RUN_TB}_run
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cp $${DESIGN_NAME}_icv_in_design.pt.v ./$${RUN_TB}_run/$${DESIGN_NAME}_cocosim.v
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TaskDir=`readlink -f ../*_Verilog/TaskConfigCopy`
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TaskDir2=`readlink -f ../*_task`
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if [ -d "$$TaskDir" ]; then
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rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run
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elif [ -d "$$TaskDir2" ]; then
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TaskDir=`readlink -f ../*_task`
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rm -rf ./$${RUN_TB}_run/TaskConfigCopy && ln -s $${TaskDir} ./$${RUN_TB}_run/TaskConfigCopy
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else
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echo "Task configuration directory not found"
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fi
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# = = = = = = = = = = = Enter Run Directory = = = = = = = = = = = = =
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cd $${RUN_TB}_run
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cp ../INIT/$${INCLUDE_POSTPNR}.v ./fabric_netlists_cocosim.v
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echo "\`include \"$$(readlink -f $${DESIGN_NAME}_cocosim.v)\"" >> ./fabric_netlists_cocosim.v
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# = = = = = = = = = = = Insert Init Signals = = = = = = = = = = = =
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if test -f "../INIT/$${RUN_TB}_init.v"; then
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echo "Found Initialization file [../INIT/$${RUN_TB}_init.v]"
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modLineNo=$$(grep -n "module fpga_top" $${DESIGN_NAME}_cocosim.v | cut -f1 -d:)
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echo $${modLineNo}
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sed -i "$${modLineNo},\$${/endmodule/d}" $${DESIGN_NAME}_cocosim.v
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cat ../INIT/$${RUN_TB}_init.v >> $${DESIGN_NAME}_cocosim.v
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printf "\nendmodule" >> $${DESIGN_NAME}_cocosim.v
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else
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echo "No Initialization file found [../INIT/$${RUN_TB}_init.v]"
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fi
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# = = = = = = = = Create Makefile to run = = = = = = = = = = = = = =
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echo "TOPLEVEL_LANG = verilog" > Makefile
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echo "VERILOG_SOURCES = fabric_netlists_cocosim.v" >> Makefile
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echo "TOPLEVEL = $${DESIGN_NAME}" >> Makefile
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echo "MODULE = $${VerificationFile}" >> Makefile
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echo "TESTCASE = $${RUN_TB}" >> Makefile
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echo "" >> Makefile
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echo "include $(shell cocotb-config --makefiles)/Makefile.sim" >> Makefile
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break
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done
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if [ -z "$$DRY_RUN" ]; then make SIM=$${SIM:-${SIM}}; fi
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