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SOFA/FPGA1212_SOFA_CHD_PNR
History
Ganesh Gore 9f9897c5e2 [SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending 2020-12-14 00:34:42 -07:00
..
FPGA1212_SOFA_CHD_Verilog [SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending 2020-12-14 00:34:42 -07:00
FPGA1212_SOFA_CHD_task [SOFA_CHD] Added OpenFPGA taks and verilog netlist 2020-12-09 00:49:00 -07:00
Verification [SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending 2020-12-14 00:34:42 -07:00
fpga_top [SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending 2020-12-14 00:34:42 -07:00
README.md [SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending 2020-12-14 00:34:42 -07:00
config.sh [SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending 2020-12-14 00:34:42 -07:00

README.md

FPGA1212_SOFA_CHD_PNR

https://skywater-openfpga.readthedocs.io/en/latest/datasheet/qlsofa_hd/