5 Commits

Author	SHA1	Message	Date
tangxifan	4875b2de95	[HDL] Patch pin assignment names to be consistent with post-PnR netlists	2020-12-02 14:02:18 -07:00
tangxifan	a900cba5a5	[HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail	2020-11-30 10:29:05 -07:00
tangxifan	78addbe294	[HDL] Name fix to be compatible with testbench generation	2020-11-29 21:01:44 -07:00
tangxifan	fcee5f1c91	[HDL] Typo fix in pin assignment description	2020-11-29 18:02:26 -07:00
tangxifan	de5411db6b	[HDL] Add pin assignement for v1.1 HD FPGA	2020-11-29 12:58:53 -07:00