18 Commits

Author	SHA1	Message	Date
tangxifan	55db5d5aaf	[Arch] Revert to the classical pin location in vpr arch	2020-11-17 15:09:31 -07:00
tangxifan	22d0aaafeb	[Arch] Move global pins to the first of pin list in vpr architecture to ease backend scripts	2020-11-17 11:47:47 -07:00
tangxifan	290b1f47a0	[Arch] Change I/O density to interface wishbone	2020-11-13 17:44:53 -07:00
tangxifan	be33082faf	[Arch] Remove out-of-data architectures	2020-11-13 09:50:45 -07:00
tangxifan	bbf871d22a	[Arch] Limit shift register chain only to columns of clbs	2020-11-13 09:39:59 -07:00
tangxifan	5d3b08ada4	[Arch] Rename ports to be consistent with backend scripts and remove shift-register chain across fabric	2020-11-13 09:24:57 -07:00
tangxifan	16af5e6ad8	[Arch] Minor change to keep a regular arch in fle->lut connection	2020-11-09 15:52:46 -07:00
tangxifan	630c4060a8	[Arch] Detect some bugs (will not cause verification failed) in vpr arch	2020-11-09 15:12:00 -07:00
tangxifan	6811604e5c	[Arch] Revert back to a lower Fc for area efficiency	2020-11-05 22:23:11 -07:00
tangxifan	fe3bf8ba58	[Arch] Patch to have UNIQUE routing blocks	2020-11-05 22:20:51 -07:00
tangxifan	1892dd5205	[Arch] Minor patch on arch to force unique CBY	2020-11-05 21:55:43 -07:00
tangxifan	5b69b0a087	[Arch] Add the VPR architecture tuned for Caravel I/O interface	2020-11-05 09:43:38 -07:00
tangxifan	c26f8a5aac	[Arch] Add architecture files for embedded FPGA IP	2020-11-02 19:55:40 -07:00
tangxifan	bff4fdfdc1	[Arch] Update pin equivalence for the non-LR non-adder k4 arch	2020-11-02 11:27:44 -07:00
tangxifan	af4b89b37c	[Arch] Bug fix in non-adder k4 arch	2020-10-24 12:00:20 -06:00
tangxifan	bd834d4086	[Arch] Add a simplified k4 architecture without hard adders	2020-10-24 11:37:04 -06:00
tangxifan	cee0fa601e	[Documentation] Add README for subdirectories	2020-10-09 22:36:43 -06:00
tangxifan	c5d6bcd15f	[Architecture] Add VPR and OpenFPGA architecture description which is binded to skywater 130nm sclib	2020-10-09 14:33:42 -06:00