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SOFA
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6 Commits 16 Branches 1 Tag 1.8 GiB
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3 Commits

Author SHA1 Message Date
tangxifan a2b42c2e5f [Script] Now use variables to redirect the output directory of Verilog/SDC files 2020-10-09 16:00:41 -06:00
tangxifan b9cbe3c69e [Flow] Add openfpga task for generate fabric 2020-10-09 15:07:18 -06:00
tangxifan 64bbaf374d [Flow] Add scripts to run OpenFPGA tasks 2020-10-09 14:49:54 -06:00