7 Commits

Author	SHA1	Message	Date
tangxifan	5b69b0a087	[Arch] Add the VPR architecture tuned for Caravel I/O interface	2020-11-05 09:43:38 -07:00
tangxifan	c26f8a5aac	[Arch] Add architecture files for embedded FPGA IP	2020-11-02 19:55:40 -07:00
tangxifan	bff4fdfdc1	[Arch] Update pin equivalence for the non-LR non-adder k4 arch	2020-11-02 11:27:44 -07:00
tangxifan	af4b89b37c	[Arch] Bug fix in non-adder k4 arch	2020-10-24 12:00:20 -06:00
tangxifan	bd834d4086	[Arch] Add a simplified k4 architecture without hard adders	2020-10-24 11:37:04 -06:00
tangxifan	cee0fa601e	[Documentation] Add README for subdirectories	2020-10-09 22:36:43 -06:00
tangxifan	c5d6bcd15f	[Architecture] Add VPR and OpenFPGA architecture description which is binded to skywater 130nm sclib	2020-10-09 14:33:42 -06:00