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SOFA
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67 Commits 16 Branches 1 Tag 1.8 GiB
Commit Graph

21 Commits

Author SHA1 Message Date
tangxifan a25b8252f3 [Arch] Add openfpga arch template for the caravel 2020-11-05 10:20:54 -07:00
tangxifan 5b69b0a087 [Arch] Add the VPR architecture tuned for Caravel I/O interface 2020-11-05 09:43:38 -07:00
tangxifan 1264054cab [Arch] Bug fix in netlist path 2020-11-03 09:57:25 -07:00
tangxifan 48d8f8b664 [Arch] Same patch on the scff on another arch 2020-11-03 09:54:30 -07:00
tangxifan 533a6ab90f [Arch] Use an exact fit scan-chain flip-flop in the architectures 2020-11-03 09:53:16 -07:00
tangxifan b5c781f555 [Arch] Patch the HDL netlist name to differetiate between cell types 2020-11-03 09:17:22 -07:00
tangxifan 40ca8dfbe3 [Arch] Update architecture files to use the wrapper files 2020-11-03 09:14:47 -07:00
tangxifan c26f8a5aac [Arch] Add architecture files for embedded FPGA IP 2020-11-02 19:55:40 -07:00
tangxifan bff4fdfdc1 [Arch] Update pin equivalence for the non-LR non-adder k4 arch 2020-11-02 11:27:44 -07:00
tangxifan 23ac6af11f [Arch] Bug fix on the wrong verilog netlist path 2020-11-01 15:45:41 -07:00
tangxifan af4b89b37c [Arch] Bug fix in non-adder k4 arch 2020-10-24 12:00:20 -06:00
tangxifan eaf5ba6074 [Arch] Add openfpga arch for non-adder k4 vpr arch 2020-10-24 11:44:41 -06:00
tangxifan bd834d4086 [Arch] Add a simplified k4 architecture without hard adders 2020-10-24 11:37:04 -06:00
tangxifan 5e6a6d1e53 [Architecture] Add a set of openfpga architectures using different Skywater Foundry standard cells 2020-10-14 09:11:05 -06:00
tangxifan 14050bba26 [Architecture] Add OpenFPGA architecture which is binded to the open-source ms sclib 2020-10-10 19:16:35 -06:00
tangxifan cee0fa601e [Documentation] Add README for subdirectories 2020-10-09 22:36:43 -06:00
tangxifan 8b5a17457c [Architecture] bug fix in openfpga arch 2020-10-09 20:30:51 -06:00
tangxifan 0053c57954 [Arch] Update architecture file 2020-10-09 18:32:31 -06:00
tangxifan 069c36cbfc [Architecture] Create template architecture for openfpga 2020-10-09 17:28:14 -06:00
tangxifan 241aae76e4 [Architecture] Rename architecture file 2020-10-09 15:04:21 -06:00
tangxifan c5d6bcd15f [Architecture] Add VPR and OpenFPGA architecture description which is binded to skywater 130nm sclib 2020-10-09 14:33:42 -06:00