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SOFA
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138 Commits 16 Branches 1 Tag 1.8 GiB
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3 Commits

Author SHA1 Message Date
tangxifan 625ad5e9c6 [HDL] Alpha version of behavioral-level Verilog for SoC wrapper 2020-11-13 18:34:40 -07:00
tangxifan 5f02463098 [HDL] Update wrapper for caravel SoC interface 2020-11-12 19:06:49 -07:00
tangxifan ae97e4424d [HDL] Add wrapper for Caravel interface 2020-11-07 22:42:29 -07:00