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2 Commits

Author SHA1 Message Date
Ganesh Gore 82767cd1b2 Updated 12x12 design skipped module GDSs 2020-11-10 15:37:00 -07:00
Ganesh Gore ec9a02f9e0 Added 12x12 FPGA design with SKY130_SC_HD cells 2020-10-28 12:41:37 -06:00