4 Commits

Author	SHA1	Message	Date
tangxifan	ae97e4424d	[HDL] Add wrapper for Caravel interface	2020-11-07 22:42:29 -07:00
tangxifan	e952eb951d	[HDL] Add preprocessing flags for running functional verification	2020-11-05 11:29:23 -07:00
tangxifan	64d1113461	[HDL] Add HDL codes for the FPGA I/O cell tuned for Caravel	2020-11-05 10:18:52 -07:00
tangxifan	12881d7a31	[HDL] Move verilog wrapper to HDL directory	2020-11-03 09:19:43 -07:00