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SOFA
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386 Commits 16 Branches 1 Tag 1.8 GiB
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2 Commits

Author SHA1 Message Date
tangxifan b966829566 [Script] Force a fixed number of clock cycles in simulation to avoid false-positive 2020-12-02 17:50:23 -07:00
tangxifan cbd9239e41 [Script] Add custom simulation settings for the Skywater 130nm eFPGA fabric 2020-11-17 14:57:23 -07:00