9 Commits

Author	SHA1	Message	Date
Ganesh Gore	f385c0ca11	[FPGA1212_v1.1] Added OpenFPGA task and verilog netlist	2020-12-02 01:43:05 -07:00
tangxifan	cdfa3d5ff4	[HDL] Update wrapper using the new generator	2020-11-29 12:47:52 -07:00
tangxifan	b08b77994c	[HDL] Bug fix in the wrapper generator; now Wishbone clock is wired to a gpio of FPGA	2020-11-20 18:13:37 -07:00
tangxifan	6fa5e935fa	[HDL] Update wrapper generator to use tri-state buffer for outputs	2020-11-19 17:14:50 -07:00
Ganesh Gore	37e72cffb5	[HDL] Updated wrapper generation script	2020-11-18 23:15:26 -07:00
tangxifan	014a6b56ce	[HDL] Add clock switch to wrapper	2020-11-18 20:50:10 -07:00
tangxifan	33824bf179	[HDL] Update caravel wrapper for new I/O assignment	2020-11-18 20:44:54 -07:00
tangxifan	a916ce7e03	[HDL] Bug fix in the caravel fpga wrapper built with hd cell library	2020-11-18 11:29:37 -07:00
tangxifan	d36cb8abe7	[HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script	2020-11-17 21:44:13 -07:00