13 Commits

Author	SHA1	Message	Date
tangxifan	d0f9ca718d	[HDL] bug fix in wrapper line generator	2020-11-29 12:47:22 -07:00
tangxifan	9f82d9bf54	[HDL] Correct typo in wrapper generator	2020-11-29 12:39:56 -07:00
tangxifan	f78a53fd03	[HDL] Add tab to wrapper line generation	2020-11-29 12:35:24 -07:00
tangxifan	ebd3053a4e	[HDL] bug fix in wrapper generator	2020-11-29 12:31:32 -07:00
tangxifan	0e964534bc	[HDL] bug fix in wrapper line generator	2020-11-29 12:01:15 -07:00
tangxifan	27da78fe29	[HDL] Update wrapper line generator to parse json data	2020-11-29 11:57:34 -07:00
tangxifan	bc3d839e5b	[HDL] Upgrading code generator for wrapper	2020-11-29 10:35:10 -07:00
tangxifan	b08b77994c	[HDL] Bug fix in the wrapper generator; now Wishbone clock is wired to a gpio of FPGA	2020-11-20 18:13:37 -07:00
tangxifan	6fa5e935fa	[HDL] Update wrapper generator to use tri-state buffer for outputs	2020-11-19 17:14:50 -07:00
Ganesh Gore	37e72cffb5	[HDL] Updated wrapper generation script	2020-11-18 23:15:26 -07:00
tangxifan	33824bf179	[HDL] Update caravel wrapper for new I/O assignment	2020-11-18 20:44:54 -07:00
tangxifan	a916ce7e03	[HDL] Bug fix in the caravel fpga wrapper built with hd cell library	2020-11-18 11:29:37 -07:00
tangxifan	d36cb8abe7	[HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script	2020-11-17 21:44:13 -07:00