40 Commits

Author	SHA1	Message	Date
Ganesh Gore	f385c0ca11	[FPGA1212_v1.1] Added OpenFPGA task and verilog netlist	2020-12-02 01:43:05 -07:00
tangxifan	a900cba5a5	[HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail	2020-11-30 10:29:05 -07:00
tangxifan	78addbe294	[HDL] Name fix to be compatible with testbench generation	2020-11-29 21:01:44 -07:00
tangxifan	fcee5f1c91	[HDL] Typo fix in pin assignment description	2020-11-29 18:02:26 -07:00
tangxifan	de5411db6b	[HDL] Add pin assignement for v1.1 HD FPGA	2020-11-29 12:58:53 -07:00
tangxifan	cdfa3d5ff4	[HDL] Update wrapper using the new generator	2020-11-29 12:47:52 -07:00
tangxifan	d0f9ca718d	[HDL] bug fix in wrapper line generator	2020-11-29 12:47:22 -07:00
tangxifan	9f82d9bf54	[HDL] Correct typo in wrapper generator	2020-11-29 12:39:56 -07:00
tangxifan	899018d503	[HDL] Bug fix in wrapper template	2020-11-29 12:38:25 -07:00
tangxifan	ea758cd5b1	[HDL] Update wrapper template as most codes can be auto-generated	2020-11-29 12:36:23 -07:00
tangxifan	f78a53fd03	[HDL] Add tab to wrapper line generation	2020-11-29 12:35:24 -07:00
tangxifan	ebd3053a4e	[HDL] bug fix in wrapper generator	2020-11-29 12:31:32 -07:00
tangxifan	0e964534bc	[HDL] bug fix in wrapper line generator	2020-11-29 12:01:15 -07:00
tangxifan	9622b44554	[HDL] Bug fix in JSON file syntax	2020-11-29 11:59:56 -07:00
tangxifan	27da78fe29	[HDL] Update wrapper line generator to parse json data	2020-11-29 11:57:34 -07:00
tangxifan	bc3d839e5b	[HDL] Upgrading code generator for wrapper	2020-11-29 10:35:10 -07:00
tangxifan	aac8ddc3ec	[HDL] update json to ease parsing	2020-11-28 21:10:46 -07:00
tangxifan	47389a483e	[HDL] Add json description for pin assignment v1.0	2020-11-28 20:55:41 -07:00
tangxifan	aff43bf473	[Doc] Add README to HDL common files	2020-11-28 17:37:36 -07:00
tangxifan	31dcd4a17f	[HDL] Add a wrapper for HD MUX2 cell required by carry logic	2020-11-27 16:01:27 -07:00
tangxifan	b08b77994c	[HDL] Bug fix in the wrapper generator; now Wishbone clock is wired to a gpio of FPGA	2020-11-20 18:13:37 -07:00
tangxifan	6fa5e935fa	[HDL] Update wrapper generator to use tri-state buffer for outputs	2020-11-19 17:14:50 -07:00
tangxifan	dde0656968	[HDL] Patch tech mapped netlists of digital I/O and remove the out-of-date behavoiral codes	2020-11-19 16:31:06 -07:00
Ganesh Gore	37e72cffb5	[HDL] Updated wrapper generation script	2020-11-18 23:15:26 -07:00
tangxifan	014a6b56ce	[HDL] Add clock switch to wrapper	2020-11-18 20:50:10 -07:00
tangxifan	33824bf179	[HDL] Update caravel wrapper for new I/O assignment	2020-11-18 20:44:54 -07:00
tangxifan	ce91890a0e	[HDL] Now use a proper drive strength of 4 in the digital I/O cells	2020-11-18 11:58:21 -07:00
tangxifan	4837e6d424	[HDL] Remove out-of-data wrapper	2020-11-18 11:30:53 -07:00
tangxifan	a916ce7e03	[HDL] Bug fix in the caravel fpga wrapper built with hd cell library	2020-11-18 11:29:37 -07:00
tangxifan	d36cb8abe7	[HDL] Add behavoiral and tech-mapped caravel wrapper Verilog codes and code generator script	2020-11-17 21:44:13 -07:00
tangxifan	58440b8c42	[HDL] Bug fix in I/O cell	2020-11-17 20:03:20 -07:00
tangxifan	8803b30b26	[HDL] Rename por of I/O cell to be consistent with documentation	2020-11-17 19:33:53 -07:00
tangxifan	5415af07cc	[HDL] Add digitial I/O with protection circuitry	2020-11-17 19:17:48 -07:00
tangxifan	625ad5e9c6	[HDL] Alpha version of behavioral-level Verilog for SoC wrapper	2020-11-13 18:34:40 -07:00
tangxifan	80655c5869	[HDL] Digital I/O of embedded FPGA is now lib independent	2020-11-13 10:00:30 -07:00
tangxifan	5f02463098	[HDL] Update wrapper for caravel SoC interface	2020-11-12 19:06:49 -07:00
tangxifan	ae97e4424d	[HDL] Add wrapper for Caravel interface	2020-11-07 22:42:29 -07:00
tangxifan	e952eb951d	[HDL] Add preprocessing flags for running functional verification	2020-11-05 11:29:23 -07:00
tangxifan	64d1113461	[HDL] Add HDL codes for the FPGA I/O cell tuned for Caravel	2020-11-05 10:18:52 -07:00
tangxifan	12881d7a31	[HDL] Move verilog wrapper to HDL directory	2020-11-03 09:19:43 -07:00