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SOFA
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11 Commits 16 Branches 1 Tag 1.8 GiB
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4 Commits

Author SHA1 Message Date
tangxifan 070b0314fd [Script] Reduce hierarchy level of task configuration files 2020-10-09 20:21:41 -06:00
tangxifan 64043218eb [Script] Add openfpga task template 2020-10-09 20:11:12 -06:00
tangxifan a2b42c2e5f [Script] Now use variables to redirect the output directory of Verilog/SDC files 2020-10-09 16:00:41 -06:00
tangxifan b9cbe3c69e [Flow] Add openfpga task for generate fabric 2020-10-09 15:07:18 -06:00