8 Commits

Author	SHA1	Message	Date
tangxifan	dde0656968	[HDL] Patch tech mapped netlists of digital I/O and remove the out-of-date behavoiral codes	2020-11-19 16:31:06 -07:00
tangxifan	ce91890a0e	[HDL] Now use a proper drive strength of 4 in the digital I/O cells	2020-11-18 11:58:21 -07:00
tangxifan	58440b8c42	[HDL] Bug fix in I/O cell	2020-11-17 20:03:20 -07:00
tangxifan	8803b30b26	[HDL] Rename por of I/O cell to be consistent with documentation	2020-11-17 19:33:53 -07:00
tangxifan	5415af07cc	[HDL] Add digitial I/O with protection circuitry	2020-11-17 19:17:48 -07:00
tangxifan	80655c5869	[HDL] Digital I/O of embedded FPGA is now lib independent	2020-11-13 10:00:30 -07:00
tangxifan	64d1113461	[HDL] Add HDL codes for the FPGA I/O cell tuned for Caravel	2020-11-05 10:18:52 -07:00
tangxifan	12881d7a31	[HDL] Move verilog wrapper to HDL directory	2020-11-03 09:19:43 -07:00