[Cleanup] Renamed projects to SOFA-HD and QLSOFA-HD

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This commit is contained in:

Ganesh Gore 2020-12-14 00:45:11 -07:00

parent 9f9897c5e2

commit fa87753d62

335 changed files with 0 additions and 75238 deletions

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC

top_top_formal_verification.v

FPGA1212_QLSOFA_HD_PNR

FPGA1212_RESET_HD_SKY_Verilog

OpenFPGAEngine.info

SDC

disable_configure_ports.sdc

SRC

InstancesMap.txtdefine_simulation.vfabric_netlists.vfpga_core.vfpga_defines.vfpga_top.v

lb

grid_clb.vlogical_tile_clb_mode_clb_.vlogical_tile_clb_mode_default__fle.vlogical_tile_clb_mode_default__fle_mode_physical__fabric.vlogical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.vlogical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.vlogical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.vlogical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.vlogical_tile_io_mode_io_.vlogical_tile_io_mode_physical__iopad.v

routing

cbx_1__0_.vcbx_1__1_.vcbx_1__2_.vcby_0__1_.vcby_1__1_.vcby_2__1_.vsb_0__0_.vsb_0__1_.vsb_0__2_.vsb_1__0_.vsb_1__1_.vsb_1__2_.vsb_2__0_.vsb_2__1_.vsb_2__2_.v

sub_module

arch_encoder.vdigital_io_hd.vfpga_top.vinv_buf_passgate.vlocal_encoder.vluts.vmemories.vmuxes.vsky130_fd_sc_hd_wrapper .vwires.v

top_include_netlists.v

TESTBENCH/top

fabric_bitstream.bitfabric_bitstream.xmlfabric_indepenent_bitstream.xml

Testbench_Case

case_top.tcl

openfpgashell.logproj_const.tcl

scandef

cbx_1__0__scandef.defcbx_1__1__scandef.defcbx_1__2__scandef.defcby_0__1__scandef.defcby_1__1__scandef.defcby_2__1__scandef.defgrid_clb_scandef.defsb_0__0__scandef.defsb_0__1__scandef.defsb_0__2__scandef.defsb_1__0__scandef.defsb_1__1__scandef.defsb_1__2__scandef.defsb_2__0__scandef.defsb_2__1__scandef.defsb_2__2__scandef.def

FPGA1212_RESET_HD_SKY_task

arch

fabric_key.xmlopenfpga_arch.xmlvpr_arch.xml

config

task.conftask_generation.conftask_simulation.conf

design_variables.ymlgenerate_fabric.openfpgagenerate_testbench.openfpga

micro_benchmark

and.actand.blifand.v

process_top_def.sh

sc_verilog

digital_io_hd.vfpga_top.vsky130_fd_sc_hd_wrapper .v

user_project_wrapper_empty.defuser_project_wrapper_template.def

fpga_top

Screenshots

ConfigFlipFLop.pngConfigurationChain.pngProgClockTree.pngclockTree.pngmet1_utilization.pngmet2_utilization.pngmet3_utilization.pngmet4_utilization.pngpower_contacts.pngutilization.png

fpga_top_icv_in_design.fm.vfpga_top_icv_in_design.gds.gzfpga_top_icv_in_design.leffpga_top_icv_in_design.lvs.vfpga_top_icv_in_design.nominal_25.spef

Show More

33666

FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/top_top_formal_verification.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/OpenFPGAEngine.info → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/OpenFPGAEngine.info

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_configure_ports.sdc → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_configure_ports.sdc

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/InstancesMap.txt → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/InstancesMap.txt

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/define_simulation.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/define_simulation.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fabric_netlists.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fabric_netlists.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fpga_core.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fpga_core.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/fpga_defines.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fpga_defines.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fpga_top.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fpga_top.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/grid_clb.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/grid_clb.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cbx_1__0_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cbx_1__0_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cbx_1__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cbx_1__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cbx_1__2_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cbx_1__2_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cby_0__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cby_0__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cby_1__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cby_1__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cby_2__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cby_2__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_0__0_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_0__0_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_0__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_0__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_0__2_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_0__2_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_1__0_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_1__0_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_1__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_1__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_1__2_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_1__2_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_2__0_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_2__0_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_2__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_2__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_2__2_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_2__2_.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/sub_module/arch_encoder.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/arch_encoder.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/sub_module/digital_io_hd.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/digital_io_hd.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/fpga_top.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/fpga_top.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/sub_module/inv_buf_passgate.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/inv_buf_passgate.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/sub_module/local_encoder.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/local_encoder.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/luts.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/luts.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/memories.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/memories.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/muxes.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/muxes.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/sky130_fd_sc_hd_wrapper .v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/sky130_fd_sc_hd_wrapper .v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/sub_module/wires.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/wires.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/top_include_netlists.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/top_include_netlists.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/Testbench_Case/case_top.tcl → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/Testbench_Case/case_top.tcl

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/openfpgashell.log → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/openfpgashell.log

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/proj_const.tcl → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/proj_const.tcl

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cbx_1__0__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/cbx_1__0__scandef.def

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cbx_1__1__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/cbx_1__1__scandef.def

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cbx_1__2__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/cbx_1__2__scandef.def

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cby_0__1__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/cby_0__1__scandef.def

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cby_1__1__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/cby_1__1__scandef.def

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cby_2__1__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/cby_2__1__scandef.def

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/grid_clb_scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/grid_clb_scandef.def

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_0__0__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_0__0__scandef.def

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/arch/fabric_key.xml → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/arch/fabric_key.xml

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_task/arch/openfpga_arch.xml → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/arch/openfpga_arch.xml

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/process_top_def.sh → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/process_top_def.sh

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/sc_verilog/digital_io_hd.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/sc_verilog/digital_io_hd.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_task/sc_verilog/sky130_fd_sc_hd_wrapper .v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/sc_verilog/sky130_fd_sc_hd_wrapper .v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/user_project_wrapper_empty.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/user_project_wrapper_empty.def

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FPGA1212_RESET_HD_SKY_PNR/fpga_top/Screenshots/ConfigFlipFLop.png → FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ConfigFlipFLop.png

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FPGA1212_RESET_HD_SKY_PNR/fpga_top/Screenshots/met1_utilization.png → FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met1_utilization.png

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FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.fm.v → FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.fm.v

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FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.gds.gz → FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz

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FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef → FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef

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