Added sample pin constraint run

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/and2.pcf

@@ -0,0 +1,3 @@
+set_io a gfpga_pad_io_soc_in[0]
+set_io b gfpga_pad_io_soc_in[1]
+set_io c gfpga_pad_io_soc_out[6]

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/and_fix_pins.place

@@ -0,0 +1,3 @@
+a	    0	1	0
+b	    2	0	3
+out:c	1	3	7

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_generation.conf

@@ -23,6 +23,11 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
 external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
 openfpga_vpr_device_layout=FPGA88
 openfpga_vpr_route_chan_width=60
+openfpga_pcf=${PATH:TASK_DIR}/and2.pcf
+openfpga_pin_table=${PATH:TASK_DIR}/pinmap_sofa_a.csv
+openfpga_io_coordinate_file=${PATH:TASK_DIR}/fpga_io_coordinate.xml
+openfpga_vpr_fix_pins_file=and2_fix_pins.place
+openfpga_pin_table_direction_convention=explicit
 
 [ARCHITECTURES]
 arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_simulation.conf

@@ -1,4 +1,4 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+    # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 # Configuration file for running experiments
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
@@ -8,12 +8,11 @@
 
 [GENERAL]
 run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
-power_analysis = true
 spice_output=false
 verilog_output=true
-timeout_each_job = 1*60
+timeout_each_job = 20*60
-fpga_flow=yosys_vpr
+fpga_flow=vpr_blif
 arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
 
 
@@ -24,15 +23,22 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
 external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
 openfpga_vpr_device_layout=FPGA88
 openfpga_vpr_route_chan_width=60
+openfpga_pcf=${PATH:TASK_DIR}/and2.pcf
+openfpga_pin_table=${PATH:TASK_DIR}/pinmap_sofa_a.csv
+openfpga_io_map_file=${PATH:TASK_DIR}/fpga_io_location.xml
+openfpga_vpr_fix_pins_file=and2_fix_pins.place
+openfpga_pin_table_direction_convention=explicit
 
 [ARCHITECTURES]
 arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
 
 [BENCHMARKS]
-bench0=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v
+bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = counter
+bench0_top = top
+bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
+bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-#end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/fpga_io_location.xml

@@ -0,0 +1,263 @@
+<!--
+	- FPGA Fabric I/O Information
+	- Generated by OpenFPGA
+-->
+
+<io_coordinates>
+    <io pad="gfpga_pad_io_soc_in[96]" x="0" y="1" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[96]" x="0" y="1" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[97]" x="0" y="1" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[97]" x="0" y="1" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[98]" x="0" y="1" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[98]" x="0" y="1" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[99]" x="0" y="1" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[99]" x="0" y="1" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[100]" x="0" y="2" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[100]" x="0" y="2" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[101]" x="0" y="2" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[101]" x="0" y="2" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[102]" x="0" y="2" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[102]" x="0" y="2" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[103]" x="0" y="2" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[103]" x="0" y="2" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[104]" x="0" y="3" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[104]" x="0" y="3" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[105]" x="0" y="3" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[105]" x="0" y="3" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[106]" x="0" y="3" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[106]" x="0" y="3" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[107]" x="0" y="3" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[107]" x="0" y="3" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[108]" x="0" y="4" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[108]" x="0" y="4" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[109]" x="0" y="4" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[109]" x="0" y="4" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[110]" x="0" y="4" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[110]" x="0" y="4" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[111]" x="0" y="4" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[111]" x="0" y="4" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[112]" x="0" y="5" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[112]" x="0" y="5" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[113]" x="0" y="5" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[113]" x="0" y="5" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[114]" x="0" y="5" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[114]" x="0" y="5" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[115]" x="0" y="5" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[115]" x="0" y="5" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[116]" x="0" y="6" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[116]" x="0" y="6" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[117]" x="0" y="6" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[117]" x="0" y="6" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[118]" x="0" y="6" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[118]" x="0" y="6" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[119]" x="0" y="6" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[119]" x="0" y="6" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[120]" x="0" y="7" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[120]" x="0" y="7" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[121]" x="0" y="7" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[121]" x="0" y="7" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[122]" x="0" y="7" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[122]" x="0" y="7" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[123]" x="0" y="7" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[123]" x="0" y="7" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[124]" x="0" y="8" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[124]" x="0" y="8" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[125]" x="0" y="8" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[125]" x="0" y="8" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[126]" x="0" y="8" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[126]" x="0" y="8" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[127]" x="0" y="8" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[127]" x="0" y="8" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[92]" x="1" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[92]" x="1" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[93]" x="1" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[93]" x="1" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[94]" x="1" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[94]" x="1" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[95]" x="1" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[95]" x="1" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[0]" x="1" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[0]" x="1" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[1]" x="1" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[1]" x="1" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[2]" x="1" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[2]" x="1" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[3]" x="1" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[3]" x="1" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[88]" x="2" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[88]" x="2" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[89]" x="2" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[89]" x="2" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[90]" x="2" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[90]" x="2" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[91]" x="2" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[91]" x="2" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[4]" x="2" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[4]" x="2" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[5]" x="2" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[5]" x="2" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[6]" x="2" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[6]" x="2" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[7]" x="2" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[7]" x="2" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[84]" x="3" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[84]" x="3" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[85]" x="3" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[85]" x="3" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[86]" x="3" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[86]" x="3" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[87]" x="3" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[87]" x="3" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[8]" x="3" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[8]" x="3" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[9]" x="3" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[9]" x="3" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[10]" x="3" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[10]" x="3" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[11]" x="3" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[11]" x="3" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[80]" x="4" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[80]" x="4" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[81]" x="4" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[81]" x="4" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[82]" x="4" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[82]" x="4" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[83]" x="4" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[83]" x="4" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[12]" x="4" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[12]" x="4" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[13]" x="4" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[13]" x="4" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[14]" x="4" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[14]" x="4" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[15]" x="4" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[15]" x="4" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[76]" x="5" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[76]" x="5" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[77]" x="5" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[77]" x="5" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[78]" x="5" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[78]" x="5" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[79]" x="5" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[79]" x="5" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[16]" x="5" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[16]" x="5" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[17]" x="5" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[17]" x="5" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[18]" x="5" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[18]" x="5" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[19]" x="5" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[19]" x="5" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[72]" x="6" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[72]" x="6" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[73]" x="6" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[73]" x="6" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[74]" x="6" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[74]" x="6" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[75]" x="6" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[75]" x="6" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[20]" x="6" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[20]" x="6" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[21]" x="6" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[21]" x="6" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[22]" x="6" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[22]" x="6" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[23]" x="6" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[23]" x="6" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[68]" x="7" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[68]" x="7" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[69]" x="7" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[69]" x="7" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[70]" x="7" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[70]" x="7" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[71]" x="7" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[71]" x="7" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[24]" x="7" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[24]" x="7" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[25]" x="7" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[25]" x="7" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[26]" x="7" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[26]" x="7" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[27]" x="7" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[27]" x="7" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[64]" x="8" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[64]" x="8" y="0" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[65]" x="8" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[65]" x="8" y="0" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[66]" x="8" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[66]" x="8" y="0" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[67]" x="8" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[67]" x="8" y="0" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[28]" x="8" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[28]" x="8" y="9" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[29]" x="8" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[29]" x="8" y="9" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[30]" x="8" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[30]" x="8" y="9" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[31]" x="8" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[31]" x="8" y="9" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[60]" x="9" y="1" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[60]" x="9" y="1" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[61]" x="9" y="1" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[61]" x="9" y="1" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[62]" x="9" y="1" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[62]" x="9" y="1" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[63]" x="9" y="1" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[63]" x="9" y="1" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[56]" x="9" y="2" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[56]" x="9" y="2" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[57]" x="9" y="2" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[57]" x="9" y="2" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[58]" x="9" y="2" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[58]" x="9" y="2" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[59]" x="9" y="2" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[59]" x="9" y="2" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[52]" x="9" y="3" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[52]" x="9" y="3" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[53]" x="9" y="3" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[53]" x="9" y="3" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[54]" x="9" y="3" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[54]" x="9" y="3" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[55]" x="9" y="3" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[55]" x="9" y="3" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[48]" x="9" y="4" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[48]" x="9" y="4" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[49]" x="9" y="4" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[49]" x="9" y="4" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[50]" x="9" y="4" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[50]" x="9" y="4" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[51]" x="9" y="4" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[51]" x="9" y="4" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[44]" x="9" y="5" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[44]" x="9" y="5" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[45]" x="9" y="5" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[45]" x="9" y="5" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[46]" x="9" y="5" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[46]" x="9" y="5" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[47]" x="9" y="5" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[47]" x="9" y="5" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[40]" x="9" y="6" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[40]" x="9" y="6" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[41]" x="9" y="6" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[41]" x="9" y="6" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[42]" x="9" y="6" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[42]" x="9" y="6" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[43]" x="9" y="6" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[43]" x="9" y="6" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[36]" x="9" y="7" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[36]" x="9" y="7" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[37]" x="9" y="7" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[37]" x="9" y="7" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[38]" x="9" y="7" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[38]" x="9" y="7" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[39]" x="9" y="7" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[39]" x="9" y="7" z="3"/>
+    <io pad="gfpga_pad_io_soc_in[32]" x="9" y="8" z="0"/>
+    <io pad="gfpga_pad_io_soc_out[32]" x="9" y="8" z="0"/>
+    <io pad="gfpga_pad_io_soc_in[33]" x="9" y="8" z="1"/>
+    <io pad="gfpga_pad_io_soc_out[33]" x="9" y="8" z="1"/>
+    <io pad="gfpga_pad_io_soc_in[34]" x="9" y="8" z="2"/>
+    <io pad="gfpga_pad_io_soc_out[34]" x="9" y="8" z="2"/>
+    <io pad="gfpga_pad_io_soc_in[35]" x="9" y="8" z="3"/>
+    <io pad="gfpga_pad_io_soc_out[35]" x="9" y="8" z="3"/>
+</io_coordinates>

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_fabric.openfpga

@@ -32,6 +32,9 @@ lut_truth_table_fixup
 #  - Enable pin duplication on grid modules
 build_fabric --compress_routing #--verbose
 
+# Output I/O coordinate information
+write_fabric_io_info --file ${OPENFPGA_IO_COORDINATE_FILE} --no_time_stamp
+
 # Write the fabric hierarchy of module graph to a file
 # This is used by hierarchical PnR flows
 write_fabric_hierarchy --file ./fabric_hierarchy.txt

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_testbench.openfpga

@@ -1,12 +1,19 @@
-# This script is designed to generate Verilog testbenches
+# Convert .pcf to a .place file that VPR can accept
-# with a fixed device layout
+pcf2place --pcf ${OPENFPGA_PCF} \
-# It will only output netlists to be used by verification tools
+          --blif ${VPR_TESTBENCH_BLIF} \
-# including
+          --pin_table ${OPENFPGA_PIN_TABLE} \
-#   - Verilog testbenches, used by ModelSim
+          --fpga_io_map ${OPENFPGA_IO_MAP_FILE} \
-#   - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
+          --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE} \
-#
+          --pin_table_direction_convention ${OPENFPGA_PIN_TABLE_DIRECTION_CONVENTION}
-#--write_rr_graph example_rr_graph.xml
+
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
+# Run VPR for the 'and' design
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \
+  --clock_modeling ideal \
+  --device ${OPENFPGA_VPR_DEVICE_LAYOUT} \
+  --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} \
+  --absorb_buffer_luts off \
+  --write_rr_graph rr_graph_out.xml \
+  --skip_sync_clustering_and_routing_results on
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
@@ -30,45 +37,29 @@ lut_truth_table_fixup
 # Build the module graph
 #  - Enabled compression on routing architecture modules
 #  - Enable pin duplication on grid modules
-build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
+build_fabric --compress_routing #--verbose
+
+# Write I/O net mapping information
+write_io_mapping --file benchmark_io_mapping.xml --verbose --no_time_stamp
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
 
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
 # Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
+repack
+# --verbose
 
 # Build the bitstream
 #  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --write_file arch_bitstream.xml
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
 build_fabric_bitstream --verbose
 
 # Write fabric-dependent bitstream
-write_fabric_bitstream --file fabric_bitstream.xml --format xml
 write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
 
-# Write the Verilog testbench for FPGA fabric
+exit
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file ./SRC \
-        --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
-        --print_top_testbench \
-        --print_preconfig_top_testbench \
-        --print_simulation_ini ./SimulationDeck/simulation_deck.ini \
-        --explicit_port_mapping
-# Exclude signal initialization since it does not help simulator converge
-# due to the lack of reset pins for flip-flops
-#--include_signal_init
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file ./SDC_analysis
-
-# Finish and exit OpenFPGA
-exit
-
-# Note :
-# To run verification at the end of the flow maintain source in ./SRC directory

SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/pinmap_sofa_a.csv

@@ -0,0 +1,257 @@
+orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge
+TOP,,,,gfpga_pad_io_soc_in[0],gfpga_pad_io_soc_in[0],in,,
+TOP,,,,gfpga_pad_io_soc_in[1],gfpga_pad_io_soc_in[1],in,,
+TOP,,,,gfpga_pad_io_soc_in[2],gfpga_pad_io_soc_in[2],in,,
+TOP,,,,gfpga_pad_io_soc_in[3],gfpga_pad_io_soc_in[3],in,,
+TOP,,,,gfpga_pad_io_soc_in[4],gfpga_pad_io_soc_in[4],in,,
+TOP,,,,gfpga_pad_io_soc_in[5],gfpga_pad_io_soc_in[5],in,,
+TOP,,,,gfpga_pad_io_soc_in[6],gfpga_pad_io_soc_in[6],in,,
+TOP,,,,gfpga_pad_io_soc_in[7],gfpga_pad_io_soc_in[7],in,,
+TOP,,,,gfpga_pad_io_soc_in[8],gfpga_pad_io_soc_in[8],in,,
+TOP,,,,gfpga_pad_io_soc_in[9],gfpga_pad_io_soc_in[9],in,,
+TOP,,,,gfpga_pad_io_soc_in[10],gfpga_pad_io_soc_in[10],in,,
+TOP,,,,gfpga_pad_io_soc_in[11],gfpga_pad_io_soc_in[11],in,,
+TOP,,,,gfpga_pad_io_soc_in[12],gfpga_pad_io_soc_in[12],in,,
+TOP,,,,gfpga_pad_io_soc_in[13],gfpga_pad_io_soc_in[13],in,,
+TOP,,,,gfpga_pad_io_soc_in[14],gfpga_pad_io_soc_in[14],in,,
+TOP,,,,gfpga_pad_io_soc_in[15],gfpga_pad_io_soc_in[15],in,,
+TOP,,,,gfpga_pad_io_soc_in[16],gfpga_pad_io_soc_in[16],in,,
+TOP,,,,gfpga_pad_io_soc_in[17],gfpga_pad_io_soc_in[17],in,,
+TOP,,,,gfpga_pad_io_soc_in[18],gfpga_pad_io_soc_in[18],in,,
+TOP,,,,gfpga_pad_io_soc_in[19],gfpga_pad_io_soc_in[19],in,,
+TOP,,,,gfpga_pad_io_soc_in[20],gfpga_pad_io_soc_in[20],in,,
+TOP,,,,gfpga_pad_io_soc_in[21],gfpga_pad_io_soc_in[21],in,,
+TOP,,,,gfpga_pad_io_soc_in[22],gfpga_pad_io_soc_in[22],in,,
+TOP,,,,gfpga_pad_io_soc_in[23],gfpga_pad_io_soc_in[23],in,,
+TOP,,,,gfpga_pad_io_soc_in[24],gfpga_pad_io_soc_in[24],in,,
+TOP,,,,gfpga_pad_io_soc_in[25],gfpga_pad_io_soc_in[25],in,,
+TOP,,,,gfpga_pad_io_soc_in[26],gfpga_pad_io_soc_in[26],in,,
+TOP,,,,gfpga_pad_io_soc_in[27],gfpga_pad_io_soc_in[27],in,,
+TOP,,,,gfpga_pad_io_soc_in[28],gfpga_pad_io_soc_in[28],in,,
+TOP,,,,gfpga_pad_io_soc_in[29],gfpga_pad_io_soc_in[29],in,,
+TOP,,,,gfpga_pad_io_soc_in[30],gfpga_pad_io_soc_in[30],in,,
+TOP,,,,gfpga_pad_io_soc_in[31],gfpga_pad_io_soc_in[31],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[32],gfpga_pad_io_soc_in[32],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[33],gfpga_pad_io_soc_in[33],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[34],gfpga_pad_io_soc_in[34],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[35],gfpga_pad_io_soc_in[35],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[36],gfpga_pad_io_soc_in[36],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[37],gfpga_pad_io_soc_in[37],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[38],gfpga_pad_io_soc_in[38],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[39],gfpga_pad_io_soc_in[39],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[40],gfpga_pad_io_soc_in[40],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[41],gfpga_pad_io_soc_in[41],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[42],gfpga_pad_io_soc_in[42],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[43],gfpga_pad_io_soc_in[43],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[44],gfpga_pad_io_soc_in[44],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[45],gfpga_pad_io_soc_in[45],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[46],gfpga_pad_io_soc_in[46],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[47],gfpga_pad_io_soc_in[47],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[48],gfpga_pad_io_soc_in[48],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[49],gfpga_pad_io_soc_in[49],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[50],gfpga_pad_io_soc_in[50],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[51],gfpga_pad_io_soc_in[51],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[52],gfpga_pad_io_soc_in[52],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[53],gfpga_pad_io_soc_in[53],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[54],gfpga_pad_io_soc_in[54],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[55],gfpga_pad_io_soc_in[55],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[56],gfpga_pad_io_soc_in[56],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[57],gfpga_pad_io_soc_in[57],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[58],gfpga_pad_io_soc_in[58],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[59],gfpga_pad_io_soc_in[59],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[60],gfpga_pad_io_soc_in[60],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[61],gfpga_pad_io_soc_in[61],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[62],gfpga_pad_io_soc_in[62],in,,
+RIGHT,,,,gfpga_pad_io_soc_in[63],gfpga_pad_io_soc_in[63],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[64],gfpga_pad_io_soc_in[64],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[65],gfpga_pad_io_soc_in[65],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[66],gfpga_pad_io_soc_in[66],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[67],gfpga_pad_io_soc_in[67],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[68],gfpga_pad_io_soc_in[68],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[69],gfpga_pad_io_soc_in[69],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[70],gfpga_pad_io_soc_in[70],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[71],gfpga_pad_io_soc_in[71],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[72],gfpga_pad_io_soc_in[72],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[73],gfpga_pad_io_soc_in[73],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[74],gfpga_pad_io_soc_in[74],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[75],gfpga_pad_io_soc_in[75],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[76],gfpga_pad_io_soc_in[76],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[77],gfpga_pad_io_soc_in[77],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[78],gfpga_pad_io_soc_in[78],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[79],gfpga_pad_io_soc_in[79],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[80],gfpga_pad_io_soc_in[80],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[81],gfpga_pad_io_soc_in[81],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[82],gfpga_pad_io_soc_in[82],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[83],gfpga_pad_io_soc_in[83],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[84],gfpga_pad_io_soc_in[84],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[85],gfpga_pad_io_soc_in[85],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[86],gfpga_pad_io_soc_in[86],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[87],gfpga_pad_io_soc_in[87],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[88],gfpga_pad_io_soc_in[88],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[89],gfpga_pad_io_soc_in[89],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[90],gfpga_pad_io_soc_in[90],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[91],gfpga_pad_io_soc_in[91],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[92],gfpga_pad_io_soc_in[92],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[93],gfpga_pad_io_soc_in[93],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[94],gfpga_pad_io_soc_in[94],in,,
+BOTTOM,,,,gfpga_pad_io_soc_in[95],gfpga_pad_io_soc_in[95],in,,
+LEFT,,,,gfpga_pad_io_soc_in[96],gfpga_pad_io_soc_in[96],in,,
+LEFT,,,,gfpga_pad_io_soc_in[97],gfpga_pad_io_soc_in[97],in,,
+LEFT,,,,gfpga_pad_io_soc_in[98],gfpga_pad_io_soc_in[98],in,,
+LEFT,,,,gfpga_pad_io_soc_in[99],gfpga_pad_io_soc_in[99],in,,
+LEFT,,,,gfpga_pad_io_soc_in[100],gfpga_pad_io_soc_in[100],in,,
+LEFT,,,,gfpga_pad_io_soc_in[101],gfpga_pad_io_soc_in[101],in,,
+LEFT,,,,gfpga_pad_io_soc_in[102],gfpga_pad_io_soc_in[102],in,,
+LEFT,,,,gfpga_pad_io_soc_in[103],gfpga_pad_io_soc_in[103],in,,
+LEFT,,,,gfpga_pad_io_soc_in[104],gfpga_pad_io_soc_in[104],in,,
+LEFT,,,,gfpga_pad_io_soc_in[105],gfpga_pad_io_soc_in[105],in,,
+LEFT,,,,gfpga_pad_io_soc_in[106],gfpga_pad_io_soc_in[106],in,,
+LEFT,,,,gfpga_pad_io_soc_in[107],gfpga_pad_io_soc_in[107],in,,
+LEFT,,,,gfpga_pad_io_soc_in[108],gfpga_pad_io_soc_in[108],in,,
+LEFT,,,,gfpga_pad_io_soc_in[109],gfpga_pad_io_soc_in[109],in,,
+LEFT,,,,gfpga_pad_io_soc_in[110],gfpga_pad_io_soc_in[110],in,,
+LEFT,,,,gfpga_pad_io_soc_in[111],gfpga_pad_io_soc_in[111],in,,
+LEFT,,,,gfpga_pad_io_soc_in[112],gfpga_pad_io_soc_in[112],in,,
+LEFT,,,,gfpga_pad_io_soc_in[113],gfpga_pad_io_soc_in[113],in,,
+LEFT,,,,gfpga_pad_io_soc_in[114],gfpga_pad_io_soc_in[114],in,,
+LEFT,,,,gfpga_pad_io_soc_in[115],gfpga_pad_io_soc_in[115],in,,
+LEFT,,,,gfpga_pad_io_soc_in[116],gfpga_pad_io_soc_in[116],in,,
+LEFT,,,,gfpga_pad_io_soc_in[117],gfpga_pad_io_soc_in[117],in,,
+LEFT,,,,gfpga_pad_io_soc_in[118],gfpga_pad_io_soc_in[118],in,,
+LEFT,,,,gfpga_pad_io_soc_in[119],gfpga_pad_io_soc_in[119],in,,
+LEFT,,,,gfpga_pad_io_soc_in[120],gfpga_pad_io_soc_in[120],in,,
+LEFT,,,,gfpga_pad_io_soc_in[121],gfpga_pad_io_soc_in[121],in,,
+LEFT,,,,gfpga_pad_io_soc_in[122],gfpga_pad_io_soc_in[122],in,,
+LEFT,,,,gfpga_pad_io_soc_in[123],gfpga_pad_io_soc_in[123],in,,
+LEFT,,,,gfpga_pad_io_soc_in[124],gfpga_pad_io_soc_in[124],in,,
+LEFT,,,,gfpga_pad_io_soc_in[125],gfpga_pad_io_soc_in[125],in,,
+LEFT,,,,gfpga_pad_io_soc_in[126],gfpga_pad_io_soc_in[126],in,,
+LEFT,,,,gfpga_pad_io_soc_in[127],gfpga_pad_io_soc_in[127],in,,
+TOP,,,,gfpga_pad_io_soc_out[0],gfpga_pad_io_soc_out[0],out,,
+TOP,,,,gfpga_pad_io_soc_out[1],gfpga_pad_io_soc_out[1],out,,
+TOP,,,,gfpga_pad_io_soc_out[2],gfpga_pad_io_soc_out[2],out,,
+TOP,,,,gfpga_pad_io_soc_out[3],gfpga_pad_io_soc_out[3],out,,
+TOP,,,,gfpga_pad_io_soc_out[4],gfpga_pad_io_soc_out[4],out,,
+TOP,,,,gfpga_pad_io_soc_out[5],gfpga_pad_io_soc_out[5],out,,
+TOP,,,,gfpga_pad_io_soc_out[6],gfpga_pad_io_soc_out[6],out,,
+TOP,,,,gfpga_pad_io_soc_out[7],gfpga_pad_io_soc_out[7],out,,
+TOP,,,,gfpga_pad_io_soc_out[8],gfpga_pad_io_soc_out[8],out,,
+TOP,,,,gfpga_pad_io_soc_out[9],gfpga_pad_io_soc_out[9],out,,
+TOP,,,,gfpga_pad_io_soc_out[10],gfpga_pad_io_soc_out[10],out,,
+TOP,,,,gfpga_pad_io_soc_out[11],gfpga_pad_io_soc_out[11],out,,
+TOP,,,,gfpga_pad_io_soc_out[12],gfpga_pad_io_soc_out[12],out,,
+TOP,,,,gfpga_pad_io_soc_out[13],gfpga_pad_io_soc_out[13],out,,
+TOP,,,,gfpga_pad_io_soc_out[14],gfpga_pad_io_soc_out[14],out,,
+TOP,,,,gfpga_pad_io_soc_out[15],gfpga_pad_io_soc_out[15],out,,
+TOP,,,,gfpga_pad_io_soc_out[16],gfpga_pad_io_soc_out[16],out,,
+TOP,,,,gfpga_pad_io_soc_out[17],gfpga_pad_io_soc_out[17],out,,
+TOP,,,,gfpga_pad_io_soc_out[18],gfpga_pad_io_soc_out[18],out,,
+TOP,,,,gfpga_pad_io_soc_out[19],gfpga_pad_io_soc_out[19],out,,
+TOP,,,,gfpga_pad_io_soc_out[20],gfpga_pad_io_soc_out[20],out,,
+TOP,,,,gfpga_pad_io_soc_out[21],gfpga_pad_io_soc_out[21],out,,
+TOP,,,,gfpga_pad_io_soc_out[22],gfpga_pad_io_soc_out[22],out,,
+TOP,,,,gfpga_pad_io_soc_out[23],gfpga_pad_io_soc_out[23],out,,
+TOP,,,,gfpga_pad_io_soc_out[24],gfpga_pad_io_soc_out[24],out,,
+TOP,,,,gfpga_pad_io_soc_out[25],gfpga_pad_io_soc_out[25],out,,
+TOP,,,,gfpga_pad_io_soc_out[26],gfpga_pad_io_soc_out[26],out,,
+TOP,,,,gfpga_pad_io_soc_out[27],gfpga_pad_io_soc_out[27],out,,
+TOP,,,,gfpga_pad_io_soc_out[28],gfpga_pad_io_soc_out[28],out,,
+TOP,,,,gfpga_pad_io_soc_out[29],gfpga_pad_io_soc_out[29],out,,
+TOP,,,,gfpga_pad_io_soc_out[30],gfpga_pad_io_soc_out[30],out,,
+TOP,,,,gfpga_pad_io_soc_out[31],gfpga_pad_io_soc_out[31],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[32],gfpga_pad_io_soc_out[32],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[33],gfpga_pad_io_soc_out[33],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[34],gfpga_pad_io_soc_out[34],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[35],gfpga_pad_io_soc_out[35],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[36],gfpga_pad_io_soc_out[36],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[37],gfpga_pad_io_soc_out[37],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[38],gfpga_pad_io_soc_out[38],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[39],gfpga_pad_io_soc_out[39],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[40],gfpga_pad_io_soc_out[40],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[41],gfpga_pad_io_soc_out[41],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[42],gfpga_pad_io_soc_out[42],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[43],gfpga_pad_io_soc_out[43],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[44],gfpga_pad_io_soc_out[44],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[45],gfpga_pad_io_soc_out[45],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[46],gfpga_pad_io_soc_out[46],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[47],gfpga_pad_io_soc_out[47],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[48],gfpga_pad_io_soc_out[48],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[49],gfpga_pad_io_soc_out[49],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[50],gfpga_pad_io_soc_out[50],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[51],gfpga_pad_io_soc_out[51],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[52],gfpga_pad_io_soc_out[52],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[53],gfpga_pad_io_soc_out[53],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[54],gfpga_pad_io_soc_out[54],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[55],gfpga_pad_io_soc_out[55],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[56],gfpga_pad_io_soc_out[56],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[57],gfpga_pad_io_soc_out[57],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[58],gfpga_pad_io_soc_out[58],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[59],gfpga_pad_io_soc_out[59],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[60],gfpga_pad_io_soc_out[60],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[61],gfpga_pad_io_soc_out[61],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[62],gfpga_pad_io_soc_out[62],out,,
+RIGHT,,,,gfpga_pad_io_soc_out[63],gfpga_pad_io_soc_out[63],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[64],gfpga_pad_io_soc_out[64],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[65],gfpga_pad_io_soc_out[65],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[66],gfpga_pad_io_soc_out[66],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[67],gfpga_pad_io_soc_out[67],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[68],gfpga_pad_io_soc_out[68],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[69],gfpga_pad_io_soc_out[69],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[70],gfpga_pad_io_soc_out[70],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[71],gfpga_pad_io_soc_out[71],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[72],gfpga_pad_io_soc_out[72],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[73],gfpga_pad_io_soc_out[73],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[74],gfpga_pad_io_soc_out[74],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[75],gfpga_pad_io_soc_out[75],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[76],gfpga_pad_io_soc_out[76],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[77],gfpga_pad_io_soc_out[77],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[78],gfpga_pad_io_soc_out[78],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[79],gfpga_pad_io_soc_out[79],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[80],gfpga_pad_io_soc_out[80],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[81],gfpga_pad_io_soc_out[81],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[82],gfpga_pad_io_soc_out[82],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[83],gfpga_pad_io_soc_out[83],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[84],gfpga_pad_io_soc_out[84],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[85],gfpga_pad_io_soc_out[85],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[86],gfpga_pad_io_soc_out[86],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[87],gfpga_pad_io_soc_out[87],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[88],gfpga_pad_io_soc_out[88],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[89],gfpga_pad_io_soc_out[89],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[90],gfpga_pad_io_soc_out[90],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[91],gfpga_pad_io_soc_out[91],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[92],gfpga_pad_io_soc_out[92],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[93],gfpga_pad_io_soc_out[93],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[94],gfpga_pad_io_soc_out[94],out,,
+BOTTOM,,,,gfpga_pad_io_soc_out[95],gfpga_pad_io_soc_out[95],out,,
+LEFT,,,,gfpga_pad_io_soc_out[96],gfpga_pad_io_soc_out[96],out,,
+LEFT,,,,gfpga_pad_io_soc_out[97],gfpga_pad_io_soc_out[97],out,,
+LEFT,,,,gfpga_pad_io_soc_out[98],gfpga_pad_io_soc_out[98],out,,
+LEFT,,,,gfpga_pad_io_soc_out[99],gfpga_pad_io_soc_out[99],out,,
+LEFT,,,,gfpga_pad_io_soc_out[100],gfpga_pad_io_soc_out[100],out,,
+LEFT,,,,gfpga_pad_io_soc_out[101],gfpga_pad_io_soc_out[101],out,,
+LEFT,,,,gfpga_pad_io_soc_out[102],gfpga_pad_io_soc_out[102],out,,
+LEFT,,,,gfpga_pad_io_soc_out[103],gfpga_pad_io_soc_out[103],out,,
+LEFT,,,,gfpga_pad_io_soc_out[104],gfpga_pad_io_soc_out[104],out,,
+LEFT,,,,gfpga_pad_io_soc_out[105],gfpga_pad_io_soc_out[105],out,,
+LEFT,,,,gfpga_pad_io_soc_out[106],gfpga_pad_io_soc_out[106],out,,
+LEFT,,,,gfpga_pad_io_soc_out[107],gfpga_pad_io_soc_out[107],out,,
+LEFT,,,,gfpga_pad_io_soc_out[108],gfpga_pad_io_soc_out[108],out,,
+LEFT,,,,gfpga_pad_io_soc_out[109],gfpga_pad_io_soc_out[109],out,,
+LEFT,,,,gfpga_pad_io_soc_out[110],gfpga_pad_io_soc_out[110],out,,
+LEFT,,,,gfpga_pad_io_soc_out[111],gfpga_pad_io_soc_out[111],out,,
+LEFT,,,,gfpga_pad_io_soc_out[112],gfpga_pad_io_soc_out[112],out,,
+LEFT,,,,gfpga_pad_io_soc_out[113],gfpga_pad_io_soc_out[113],out,,
+LEFT,,,,gfpga_pad_io_soc_out[114],gfpga_pad_io_soc_out[114],out,,
+LEFT,,,,gfpga_pad_io_soc_out[115],gfpga_pad_io_soc_out[115],out,,
+LEFT,,,,gfpga_pad_io_soc_out[116],gfpga_pad_io_soc_out[116],out,,
+LEFT,,,,gfpga_pad_io_soc_out[117],gfpga_pad_io_soc_out[117],out,,
+LEFT,,,,gfpga_pad_io_soc_out[118],gfpga_pad_io_soc_out[118],out,,
+LEFT,,,,gfpga_pad_io_soc_out[119],gfpga_pad_io_soc_out[119],out,,
+LEFT,,,,gfpga_pad_io_soc_out[120],gfpga_pad_io_soc_out[120],out,,
+LEFT,,,,gfpga_pad_io_soc_out[121],gfpga_pad_io_soc_out[121],out,,
+LEFT,,,,gfpga_pad_io_soc_out[122],gfpga_pad_io_soc_out[122],out,,
+LEFT,,,,gfpga_pad_io_soc_out[123],gfpga_pad_io_soc_out[123],out,,
+LEFT,,,,gfpga_pad_io_soc_out[124],gfpga_pad_io_soc_out[124],out,,
+LEFT,,,,gfpga_pad_io_soc_out[125],gfpga_pad_io_soc_out[125],out,,
+LEFT,,,,gfpga_pad_io_soc_out[126],gfpga_pad_io_soc_out[126],out,,
+LEFT,,,,gfpga_pad_io_soc_out[127],gfpga_pad_io_soc_out[127],out,,

openfpga-physical/Makefile

@@ -395,6 +395,7 @@ run_openfpga_sim:
 	(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp ${CONF}.conf task.conf)
 
 # =====================  Generate Netlist  =================================
+	rm -rf $${TASK_DIR_NAME}/run**
 	(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
 	run-task $${TASK_DIR_NAME} --remove_run_dir all &&
 	run-task $${TASK_DIR_NAME} ${OPTIONS})