diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/and2.pcf b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/and2.pcf new file mode 100644 index 0000000..baab3d9 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/and2.pcf @@ -0,0 +1,3 @@ +set_io a gfpga_pad_io_soc_in[0] +set_io b gfpga_pad_io_soc_in[1] +set_io c gfpga_pad_io_soc_out[6] \ No newline at end of file diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/and_fix_pins.place b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/and_fix_pins.place new file mode 100644 index 0000000..6e07ac2 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/and_fix_pins.place @@ -0,0 +1,3 @@ +a 0 1 0 +b 2 0 3 +out:c 1 3 7 \ No newline at end of file diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_generation.conf b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_generation.conf index f2dd990..24d61b6 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_generation.conf +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_generation.conf @@ -23,6 +23,11 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml openfpga_vpr_device_layout=FPGA88 openfpga_vpr_route_chan_width=60 +openfpga_pcf=${PATH:TASK_DIR}/and2.pcf +openfpga_pin_table=${PATH:TASK_DIR}/pinmap_sofa_a.csv +openfpga_io_coordinate_file=${PATH:TASK_DIR}/fpga_io_coordinate.xml +openfpga_vpr_fix_pins_file=and2_fix_pins.place +openfpga_pin_table_direction_convention=explicit [ARCHITECTURES] arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_simulation.conf b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_simulation.conf index b080fba..142ddbb 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_simulation.conf +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/config/task_simulation.conf @@ -1,4 +1,4 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Configuration file for running experiments # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs @@ -8,12 +8,11 @@ [GENERAL] run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr +timeout_each_job = 20*60 +fpga_flow=vpr_blif arch_variable_file=${PATH:TASK_DIR}/design_variables.yml @@ -24,15 +23,22 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml openfpga_vpr_device_layout=FPGA88 openfpga_vpr_route_chan_width=60 +openfpga_pcf=${PATH:TASK_DIR}/and2.pcf +openfpga_pin_table=${PATH:TASK_DIR}/pinmap_sofa_a.csv +openfpga_io_map_file=${PATH:TASK_DIR}/fpga_io_location.xml +openfpga_vpr_fix_pins_file=and2_fix_pins.place +openfpga_pin_table_direction_convention=explicit [ARCHITECTURES] arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml [BENCHMARKS] -bench0=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v +bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif [SYNTHESIS_PARAM] -bench0_top = counter +bench0_top = top +bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act +bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/fpga_io_location.xml b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/fpga_io_location.xml new file mode 100644 index 0000000..a5a47c2 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/fpga_io_location.xml @@ -0,0 +1,263 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_fabric.openfpga b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_fabric.openfpga index 427bd36..74d90c9 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_fabric.openfpga +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_fabric.openfpga @@ -32,6 +32,9 @@ lut_truth_table_fixup # - Enable pin duplication on grid modules build_fabric --compress_routing #--verbose +# Output I/O coordinate information +write_fabric_io_info --file ${OPENFPGA_IO_COORDINATE_FILE} --no_time_stamp + # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows write_fabric_hierarchy --file ./fabric_hierarchy.txt diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_testbench.openfpga b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_testbench.openfpga index 1dcf136..96a9ae1 100644 --- a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_testbench.openfpga +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/generate_testbench.openfpga @@ -1,12 +1,19 @@ -# This script is designed to generate Verilog testbenches -# with a fixed device layout -# It will only output netlists to be used by verification tools -# including -# - Verilog testbenches, used by ModelSim -# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime -# -#--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off +# Convert .pcf to a .place file that VPR can accept +pcf2place --pcf ${OPENFPGA_PCF} \ + --blif ${VPR_TESTBENCH_BLIF} \ + --pin_table ${OPENFPGA_PIN_TABLE} \ + --fpga_io_map ${OPENFPGA_IO_MAP_FILE} \ + --fpga_fix_pins ${OPENFPGA_VPR_FIX_PINS_FILE} \ + --pin_table_direction_convention ${OPENFPGA_PIN_TABLE_DIRECTION_CONVENTION} + +# Run VPR for the 'and' design +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \ + --clock_modeling ideal \ + --device ${OPENFPGA_VPR_DEVICE_LAYOUT} \ + --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} \ + --absorb_buffer_luts off \ + --write_rr_graph rr_graph_out.xml \ + --skip_sync_clustering_and_routing_results on # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -30,45 +37,29 @@ lut_truth_table_fixup # Build the module graph # - Enabled compression on routing architecture modules # - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose +build_fabric --compress_routing #--verbose + +# Write I/O net mapping information +write_io_mapping --file benchmark_io_mapping.xml --verbose --no_time_stamp + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt # Repack the netlist to physical pbs # This must be done before bitstream generator and testbench generation # Strongly recommend it is done after all the fix-up have been applied -repack #--verbose +repack +# --verbose # Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file arch_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose # Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml write_fabric_bitstream --file fabric_bitstream.bit --format plain_text -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ./SRC \ - --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ - --print_top_testbench \ - --print_preconfig_top_testbench \ - --print_simulation_ini ./SimulationDeck/simulation_deck.ini \ - --explicit_port_mapping -# Exclude signal initialization since it does not help simulator converge -# due to the lack of reset pins for flip-flops -#--include_signal_init - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ./SDC_analysis - -# Finish and exit OpenFPGA -exit - -# Note : -# To run verification at the end of the flow maintain source in ./SRC directory +exit \ No newline at end of file diff --git a/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/pinmap_sofa_a.csv b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/pinmap_sofa_a.csv new file mode 100644 index 0000000..3708f40 --- /dev/null +++ b/SOFA_A/FPGA88_SOFA_A/FPGA88_SOFA_A_task/pinmap_sofa_a.csv @@ -0,0 +1,257 @@ +orientation,row,col,pin_num_in_cell,port_name,mapped_pin,GPIO_type,Associated Clock,Clock Edge +TOP,,,,gfpga_pad_io_soc_in[0],gfpga_pad_io_soc_in[0],in,, +TOP,,,,gfpga_pad_io_soc_in[1],gfpga_pad_io_soc_in[1],in,, +TOP,,,,gfpga_pad_io_soc_in[2],gfpga_pad_io_soc_in[2],in,, +TOP,,,,gfpga_pad_io_soc_in[3],gfpga_pad_io_soc_in[3],in,, +TOP,,,,gfpga_pad_io_soc_in[4],gfpga_pad_io_soc_in[4],in,, +TOP,,,,gfpga_pad_io_soc_in[5],gfpga_pad_io_soc_in[5],in,, +TOP,,,,gfpga_pad_io_soc_in[6],gfpga_pad_io_soc_in[6],in,, +TOP,,,,gfpga_pad_io_soc_in[7],gfpga_pad_io_soc_in[7],in,, +TOP,,,,gfpga_pad_io_soc_in[8],gfpga_pad_io_soc_in[8],in,, +TOP,,,,gfpga_pad_io_soc_in[9],gfpga_pad_io_soc_in[9],in,, +TOP,,,,gfpga_pad_io_soc_in[10],gfpga_pad_io_soc_in[10],in,, +TOP,,,,gfpga_pad_io_soc_in[11],gfpga_pad_io_soc_in[11],in,, +TOP,,,,gfpga_pad_io_soc_in[12],gfpga_pad_io_soc_in[12],in,, +TOP,,,,gfpga_pad_io_soc_in[13],gfpga_pad_io_soc_in[13],in,, +TOP,,,,gfpga_pad_io_soc_in[14],gfpga_pad_io_soc_in[14],in,, +TOP,,,,gfpga_pad_io_soc_in[15],gfpga_pad_io_soc_in[15],in,, +TOP,,,,gfpga_pad_io_soc_in[16],gfpga_pad_io_soc_in[16],in,, +TOP,,,,gfpga_pad_io_soc_in[17],gfpga_pad_io_soc_in[17],in,, +TOP,,,,gfpga_pad_io_soc_in[18],gfpga_pad_io_soc_in[18],in,, +TOP,,,,gfpga_pad_io_soc_in[19],gfpga_pad_io_soc_in[19],in,, +TOP,,,,gfpga_pad_io_soc_in[20],gfpga_pad_io_soc_in[20],in,, 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+LEFT,,,,gfpga_pad_io_soc_out[103],gfpga_pad_io_soc_out[103],out,, +LEFT,,,,gfpga_pad_io_soc_out[104],gfpga_pad_io_soc_out[104],out,, +LEFT,,,,gfpga_pad_io_soc_out[105],gfpga_pad_io_soc_out[105],out,, +LEFT,,,,gfpga_pad_io_soc_out[106],gfpga_pad_io_soc_out[106],out,, +LEFT,,,,gfpga_pad_io_soc_out[107],gfpga_pad_io_soc_out[107],out,, +LEFT,,,,gfpga_pad_io_soc_out[108],gfpga_pad_io_soc_out[108],out,, +LEFT,,,,gfpga_pad_io_soc_out[109],gfpga_pad_io_soc_out[109],out,, +LEFT,,,,gfpga_pad_io_soc_out[110],gfpga_pad_io_soc_out[110],out,, +LEFT,,,,gfpga_pad_io_soc_out[111],gfpga_pad_io_soc_out[111],out,, +LEFT,,,,gfpga_pad_io_soc_out[112],gfpga_pad_io_soc_out[112],out,, +LEFT,,,,gfpga_pad_io_soc_out[113],gfpga_pad_io_soc_out[113],out,, +LEFT,,,,gfpga_pad_io_soc_out[114],gfpga_pad_io_soc_out[114],out,, +LEFT,,,,gfpga_pad_io_soc_out[115],gfpga_pad_io_soc_out[115],out,, +LEFT,,,,gfpga_pad_io_soc_out[116],gfpga_pad_io_soc_out[116],out,, +LEFT,,,,gfpga_pad_io_soc_out[117],gfpga_pad_io_soc_out[117],out,, +LEFT,,,,gfpga_pad_io_soc_out[118],gfpga_pad_io_soc_out[118],out,, +LEFT,,,,gfpga_pad_io_soc_out[119],gfpga_pad_io_soc_out[119],out,, +LEFT,,,,gfpga_pad_io_soc_out[120],gfpga_pad_io_soc_out[120],out,, +LEFT,,,,gfpga_pad_io_soc_out[121],gfpga_pad_io_soc_out[121],out,, +LEFT,,,,gfpga_pad_io_soc_out[122],gfpga_pad_io_soc_out[122],out,, +LEFT,,,,gfpga_pad_io_soc_out[123],gfpga_pad_io_soc_out[123],out,, +LEFT,,,,gfpga_pad_io_soc_out[124],gfpga_pad_io_soc_out[124],out,, +LEFT,,,,gfpga_pad_io_soc_out[125],gfpga_pad_io_soc_out[125],out,, +LEFT,,,,gfpga_pad_io_soc_out[126],gfpga_pad_io_soc_out[126],out,, +LEFT,,,,gfpga_pad_io_soc_out[127],gfpga_pad_io_soc_out[127],out,, \ No newline at end of file diff --git a/openfpga-physical/Makefile b/openfpga-physical/Makefile index 04c3678..1a8e1ef 100644 --- a/openfpga-physical/Makefile +++ b/openfpga-physical/Makefile @@ -395,6 +395,7 @@ run_openfpga_sim: (cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp ${CONF}.conf task.conf) # ===================== Generate Netlist ================================= + rm -rf $${TASK_DIR_NAME}/run** (currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir && run-task $${TASK_DIR_NAME} --remove_run_dir all && run-task $${TASK_DIR_NAME} ${OPTIONS})