Merge pull request #84 from lnis-uofu/update_task_conf

Update task conf

BENCHMARK/io_reg/io_reg.v

@@ -0,0 +1,22 @@
+module io_reg(clk, in, out);
+
+    input clk;
+    input in;
+    output out;
+    reg out;
+
+    //reg temp;
+
+    always @(posedge clk)
+    begin
+        out <= in;
+    end
+    
+    /*always @(posedge clk)
+    begin
+        out <= temp ;
+    end*/
+    
+endmodule
+
+

BENCHMARK/io_reg/io_reg_tb.v

@@ -0,0 +1,21 @@
+module io_reg_tb;
+    
+    reg clk_gen, in_gen;
+    wire out;
+
+    io_reg inst(.clk(clk_gen), .in(in_gen), .out(out));
+
+    initial begin
+        #0 in_gen = 1'b1; clk_gen = 1'b0;
+        #100 in_gen = 1'b0;
+    end
+
+    always begin
+        #10 clk_gen = ~clk_gen;
+    end
+
+    initial begin
+        #5000 $stop;
+    end
+
+endmodule

SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf

@@ -28,10 +28,11 @@ external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32
 arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
 
 [BENCHMARKS]
-bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/and2/and2.v
+bench0=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/io_reg/io_reg.v
 
 [SYNTHESIS_PARAM]
-bench0_top = and2
+bench0_top = io_reg
+bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 #end_flow_with_test=

SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf

@@ -56,7 +56,9 @@ bench22=${SKYWATER_OPENFPGA_HOME}/BENCHMARK/io_tc1/rtl/*.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
+bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
 bench1_top = and2_latch
+bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
 bench2_top = bin2bcd
 bench3_top = counter
 bench4_top = routing_test