mirror of https://github.com/lnis-uofu/SOFA.git
Merge branch 'master' into xt_dev
This commit is contained in:
tangxifan
GitHub
commit
e6c1cd24f5
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@ -11,3 +11,4 @@
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**/SRC**/*_tb.v
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**/SDC/**/*.sdc
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!**/SDC/**/disable_configure_ports.sdc
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*/runOpenFPGA
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|
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@ -1,4 +1,4 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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@ -13,21 +13,27 @@ spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=vpr_blif
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openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
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arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
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openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml
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external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
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openfpga_vpr_device_layout=12x12
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openfpga_vpr_route_chan_width=60
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml
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arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif
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bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
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[SYNTHESIS_PARAM]
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bench0_top = top
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bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v
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bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
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bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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vpr_fpga_verilog_formal_verification_top_netlist=
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@ -0,0 +1,40 @@
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##########################################################################################
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##########################################################################################
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SHELL=bash
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PYTHON_EXEC=python3.8
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RERUN = 0
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TB = top
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OPTIONS =
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.SILENT:
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.ONESHELL:
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runOpenFPGA:
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SECONDS=0
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source config.sh
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# ===================== Check Tools =====================
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which python3.8 > /dev/null
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if [ $$? -eq 1 ]; then
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echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
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fi
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# =================== Clean Previous Run =================================
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rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
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(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
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# ===================== Generate Netlist =================================
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(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
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run-task $${TASK_DIR_NAME} --remove_run_dir all
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run-task $${TASK_DIR_NAME} ${OPTIONS})
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if [ $$? -eq 1 ]; then
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echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
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fi
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duration=$$SECONDS
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date > runOpenFPGA
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echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
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clean:
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rm -rf runOpenFPGA
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@ -1,4 +1,4 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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@ -13,21 +13,27 @@ spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=vpr_blif
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openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
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arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
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openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml
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external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
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openfpga_vpr_device_layout=12x12
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openfpga_vpr_route_chan_width=60
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml
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arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif
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bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
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[SYNTHESIS_PARAM]
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bench0_top = top
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bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v
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bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
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bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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vpr_fpga_verilog_formal_verification_top_netlist=
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@ -0,0 +1,40 @@
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##########################################################################################
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##########################################################################################
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SHELL=bash
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PYTHON_EXEC=python3.8
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RERUN = 0
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TB = top
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OPTIONS =
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.SILENT:
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.ONESHELL:
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runOpenFPGA:
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SECONDS=0
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source config.sh
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# ===================== Check Tools =====================
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which python3.8 > /dev/null
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if [ $$? -eq 1 ]; then
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echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
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fi
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# =================== Clean Previous Run =================================
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rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
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(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
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# ===================== Generate Netlist =================================
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(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
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run-task $${TASK_DIR_NAME} --remove_run_dir all
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run-task $${TASK_DIR_NAME} ${OPTIONS})
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if [ $$? -eq 1 ]; then
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echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
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fi
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duration=$$SECONDS
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date > runOpenFPGA
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echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
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clean:
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rm -rf runOpenFPGA
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@ -1,4 +1,4 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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@ -13,21 +13,27 @@ spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=vpr_blif
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openfpga_shell_template=${PATH:TASK_DIR}/openfpga_flow/tasks/FPGA22_MODULAR_task/generate_testbench.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/openfpga_arch.xml
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arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:TASK_DIR}/generate_fabric.openfpga
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openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/fabric_key.xml
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external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml
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openfpga_vpr_device_layout=12x12
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openfpga_vpr_route_chan_width=40
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/arch/vpr_arch.xml
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arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.blif
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bench0=${PATH:TASK_DIR}/micro_benchmark/and.blif
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[SYNTHESIS_PARAM]
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bench0_top = top
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bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.act
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bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_MODULAR_task/micro_benchmark/and.v
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bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and.act
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bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and.v
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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vpr_fpga_verilog_formal_verification_top_netlist=
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|
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@ -0,0 +1,40 @@
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##########################################################################################
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##########################################################################################
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SHELL=bash
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PYTHON_EXEC=python3.8
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RERUN = 0
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TB = top
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OPTIONS =
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.SILENT:
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.ONESHELL:
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runOpenFPGA:
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SECONDS=0
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source config.sh
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# ===================== Check Tools =====================
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which python3.8 > /dev/null
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if [ $$? -eq 1 ]; then
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echo "xxxxxxxx Python version 3.8 is required xxxxxxxx"; exit;
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fi
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||||
# =================== Clean Previous Run =================================
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rm -f $${OPENFPGA_PATH}/openfpga_flow/tasks/$${TASK_DIR_NAME}
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(cd ./$${TASK_DIR_NAME}/config && rm -f task.conf && cp task_simulation.conf task.conf)
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# ===================== Generate Netlist =================================
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(currDir=$${PWD} && cd $$OPENFPGA_PATH && source openfpga.sh && cd $$currDir &&
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run-task $${TASK_DIR_NAME} --remove_run_dir all
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run-task $${TASK_DIR_NAME} ${OPTIONS})
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|
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if [ $$? -eq 1 ]; then
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echo "X X X X X X Failed to generate netlist X X X X X X"; exit;
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fi
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duration=$$SECONDS
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date > runOpenFPGA
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echo "$$(($$duration / 60)) minutes and $$(($$duration % 60)) seconds elapsed." >> runOpenFPGA
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clean:
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rm -rf runOpenFPGA
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47
README.md
47
README.md
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@ -21,24 +21,47 @@ This repository provide the following support for the eFPGA IPs
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|||
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||||
## Quick Start
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||||
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||||
To run the user flow using SOFA repository you need to have OpenFPGA installed.
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Please visit https://github.com/lnis-uofu/OpenFPGA#compilation for OpenFPGA installaton.
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||||
```bash
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#Clone the repository and go inside it
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git clone https://github.com/LNIS-Projects/skywater-openfpga.git
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python3 SCRIPT/repo_setup.py --openfpga_root_path ${OPENFPGA_PROJECT_DIRECTORY}
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export OPENFPGA_PATH=<path_to_openfpga_root>
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||||
# Clone the SOFA repository
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||||
git clone https://github.com/lnis-uofu/SOFA.git
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||||
|
||||
# ======== Goto specific design ========
|
||||
# FPGA1212_SOFA_CHD_PNR
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||||
# FPGA1212_QLSOFA_HD_PNR
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||||
# FPGA1212_SOFA_HD_PNR
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||||
cd FPGA1212_QLSOFA_HD_PNR
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||||
|
||||
# ======== Run example OpenFPGA Task ========
|
||||
make runOpenFPGA
|
||||
|
||||
# ======== To view the results ========
|
||||
cat FPGA1212_QLSOFA_HD_task/latest/task_result.csv
|
||||
|
||||
# ======== To view detailed log ========
|
||||
cat codeopen FPGA1212_QLSOFA_HD_task/latest/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/**/openfpgashell.log
|
||||
|
||||
```
|
||||
### To bechmark your own design
|
||||
Copy your verilog file `FPGA1212_QLSOFA_HD_task/micro_benchmark` directory
|
||||
and modify `FPGA1212_QLSOFA_HD_task/config/task_simulation.conf` file.
|
||||
|
||||
Details of different paramters can be found [Configure run_fpga_task](https://openfpga.readthedocs.io/en/latest/manual/openfpga_flow/run_fpga_task/)
|
||||
|
||||
```bash
|
||||
cd FPGA1212_QLSOFA_HD_PNR
|
||||
vi FPGA1212_QLSOFA_HD_task/config/task_simulation.conf
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
* If you have openfpga repository cloned at the same level of this project, you can simple call
|
||||
```bash
|
||||
python3 SCRIPT/repo_setup.py
|
||||
```
|
||||
|
||||
Otherwise, you should provide full path using the option _--openfpga\_root\_path_
|
||||
|
||||
|
||||
## Chip Gallery
|
||||
|
||||
You can find a chip gallery in the online documentation.
|
||||
You can find a chip gallery in the online documentation
|
||||
|
||||
## Directory Organization
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue