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Merge branch 'master' into xt_dev

This commit is contained in:
tangxifan 2021-04-03 17:49:52 -06:00 committed by GitHub
parent 9266b0fd1f 795fa021ac
commit f33777a3e9
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 3331 additions and 3 deletions
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8
.github/workflows/perform_precheck.sh vendored
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@ -8,6 +8,13 @@ cd ./${DEST_DIR}
echo "[Info] Running in directory ${PWD}"
cp ../SOFA-Chips/${SCAN_DIRECTORY}/fpga_top_icv_in_design.gds.gz ./gds/
if test -f "./gds/fpga_top_icv_in_design.gds.gz.sha1"; then
sha1sum --status -c ./gds/fpga_top_icv_in_design.gds.gz.sha1
status=$?
[ $status -eq 0 ] && echo "SHA1 matched GDS is already merged ... skipping drc" && exit
fi
fpga_top_sha1=$(sha1sum ./gds/fpga_top_icv_in_design.gds.gz)
make uncompress
echo "[Info] All files are uncompressed"
@ -80,3 +87,4 @@ if [[ 0 -eq $(git cat-file -e $CARAVEL_COMPARE_COMMIT) ]]; then
/usr/local/workspace/${DEST_DIR}/checks/compare_caravel.txt
echo "[Info] Create compare_caravel.txt"
fi
echo $fpga_top_sha1 > ./gds/fpga_top_icv_in_design.gds.gz.sha1

3318
LIB/sky130_uuopenfpga_cc_hd_tt_025C_1v80.lib Normal file
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File diff suppressed because it is too large Load Diff

3
SynRepoConfig/sync_files_qlsofa_hd.csv
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@ -1,4 +1,5 @@
SrcLoc, DestLoc
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v

1 SrcLoc, DestLoc
2 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task
3 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
4 FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
5 HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v

3
SynRepoConfig/sync_files_sofa_chd.csv
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@ -1,4 +1,5 @@
SrcLoc, DestLoc
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v

1 SrcLoc, DestLoc
2 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
3 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
4 FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
5 HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v

2
SynRepoConfig/sync_files_sofa_hd.csv
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@ -2,4 +2,4 @@ SrcLoc, DestLoc
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task
FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v
HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v

1 SrcLoc, DestLoc
2 FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task
3 FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
4 FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
5 SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v