mirror of https://github.com/lnis-uofu/SOFA.git
further changes to add 4 clock buffer tiles
This commit is contained in:
Tarachand Pagarani
parent
0b855869bc
commit
dec0a0e160
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@ -195,7 +195,7 @@
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<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
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<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/sky130_fd_sc_hd_wrapper.v">
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<circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" is_default="true" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/sky130_fd_sc_hd_wrapper.v">
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<design_technology type="cmos"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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@ -205,6 +205,14 @@
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<port type="input" prefix="cin" lib_name="S" size="1"/>
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<port type="output" prefix="cout" lib_name="X" size="1"/>
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</circuit_model>
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<circuit_model type="hard_logic" name="ckbuff_wrapper" prefix="ckbuff_wrapper" verilog_netlist="/home/tpagarani/SOFA/HDL/common/ckbuff_wrapper.v">
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<design_technology type="cmos"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" lib_name="A" size="1"/>
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<port type="output" prefix="out" lib_name="X" size="1"/>
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</circuit_model>
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</circuit_library>
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<configuration_protocol>
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<organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" num_regions="1"/>
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@ -228,8 +236,20 @@
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<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
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</direct_connection>
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<tile_annotations>
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<global_port name="clk" is_clock="true" default_val="0">
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<!--global_port name="clk" is_clock="true" default_val="0">
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<tile name="clb" port="clk[0:3]" x="-1" y="-1"/>
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</global_port-->
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<global_port name="clk[0]" default_val="0">
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<tile name="ckbuf_bottom" port="clkin_ext" x="-1" y="-1"/>
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</global_port>
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<global_port name="clk[1]" default_val="0">
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<tile name="ckbuf_right" port="clkin_ext" x="-1" y="-1"/>
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</global_port>
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<global_port name="clk[2]" default_val="0">
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<tile name="ckbuf_left" port="clkin_ext" x="-1" y="-1"/>
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</global_port>
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<global_port name="clk[3]" default_val="0">
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<tile name="ckbuf_top" port="clkin_ext" x="-1" y="-1"/>
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</global_port>
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<global_port name="Reset" is_reset="true" default_val="1">
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<tile name="clb" port="reset" x="-1" y="-1"/>
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@ -244,6 +264,16 @@
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<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block ckbuf -->
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<pb_type name="ckbuf" physical_mode_name="physical" idle_mode_name="default"/>
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<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
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<pb_type name="ckbuf[physical].ck_buff" circuit_model_name="ckbuff_wrapper"/>
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<pb_type name="ckbuf[external].CKBUFF" physical_pb_type_name="ckbuf[physical].ck_buff"/>
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<pb_type name="ckbuf[internal].CKBUFFINT" physical_pb_type_name="ckbuf[physical].ck_buff"/>
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<pb_type name="ckbuf[external].CKPAD" physical_pb_type_name="ckbuf[physical].ck_buff"/>
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<!-- End physical pb_type binding in complex block ckbuf -->
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<!-- physical pb_type binding in complex block CLB -->
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<!-- physical mode will be the default mode if not specified -->
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<pb_type name="clb.fle" physical_mode_name="physical"/>
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@ -257,7 +287,12 @@
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<port name="in" physical_mode_port="in[0:3]"/>
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<port name="out" physical_mode_port="lut4_out"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<pb_type name="clb.fle[n1_lut4].ble4.ff[VPR_FF].VPR_FF" physical_pb_type_name="clb.fle[physical].fabric.ff">
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<port name="C" physical_mode_port="clk"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut4].ble4.ff[DFF].DFF" physical_pb_type_name="clb.fle[physical].fabric.ff">
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<port name="C" physical_mode_port="clk"/>
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</pb_type>
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<!-- Binding operating pb_types in mode 'shift_register' -->
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<pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
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<!-- End physical pb_type binding in complex block IO -->
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@ -33,7 +33,25 @@
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<port name="inpad"/>
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</output_ports>
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</model>
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<model name="ck_buff">
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<input_ports>
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<port name="in" combinational_sink_ports="out"/>
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<!--port name="in"/-->
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</input_ports>
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<output_ports>
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<port name="out"/>
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</output_ports>
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</model>
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<model name="ck_buff_int">
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<input_ports>
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<port name="in" combinational_sink_ports="out"/>
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<!--port name="in"/-->
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</input_ports>
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<output_ports>
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<port name="out"/>
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</output_ports>
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</model>
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<model name="frac_lut4">
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<input_ports>
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<port name="in"/>
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@ -65,6 +83,15 @@
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<port name="Q" clock="clk"/>
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</output_ports>
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</model>
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<model name="openfpga_ff">
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<input_ports>
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<port name="D" clock="C"/>
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<port name="C" is_clock="1"/>
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</input_ports>
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<output_ports>
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<port name="Q" clock="C"/>
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</output_ports>
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</model>
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</models>
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<tiles>
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<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
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@ -123,11 +150,56 @@
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<equivalent_sites>
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<site pb_type="ckbuf"/>
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</equivalent_sites>
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<input name="clkin" num_pins="1"/>
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<input name="clkin_int" num_pins="1"/>
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<input name="clkin_ext" num_pins="1" is_non_clock_global="true"/>
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<output name="clkout" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
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<fc_override port_name="clkin_ext" fc_type="frac" fc_val="0"/>
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</fc>
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<pinlocations pattern="custom">
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<loc side="top">ckbuf.clkin ckbuf.clkout</loc>
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<loc side="top">ckbuf_bottom.clkin_int ckbuf_bottom.clkin_ext ckbuf_bottom.clkout</loc>
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</pinlocations>
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</tile>
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<tile name="ckbuf_top" capacity="1" area="0">
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<equivalent_sites>
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<site pb_type="ckbuf"/>
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</equivalent_sites>
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<input name="clkin_int" num_pins="1"/>
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<input name="clkin_ext" num_pins="1" is_non_clock_global="true"/>
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<output name="clkout" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
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<fc_override port_name="clkin_ext" fc_type="frac" fc_val="0"/>
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</fc>
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<pinlocations pattern="custom">
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<loc side="bottom">ckbuf_top.clkin_int ckbuf_top.clkin_ext ckbuf_top.clkout</loc>
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</pinlocations>
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</tile>
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<tile name="ckbuf_left" capacity="1" area="0">
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<equivalent_sites>
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<site pb_type="ckbuf"/>
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</equivalent_sites>
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<input name="clkin_int" num_pins="1"/>
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<input name="clkin_ext" num_pins="1" is_non_clock_global="true"/>
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<output name="clkout" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
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<fc_override port_name="clkin_ext" fc_type="frac" fc_val="0"/>
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</fc>
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<pinlocations pattern="custom">
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<loc side="right">ckbuf_left.clkin_int ckbuf_left.clkin_ext ckbuf_left.clkout</loc>
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</pinlocations>
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</tile>
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<tile name="ckbuf_right" capacity="1" area="0">
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<equivalent_sites>
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<site pb_type="ckbuf"/>
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</equivalent_sites>
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<input name="clkin_int" num_pins="1"/>
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<input name="clkin_ext" num_pins="1" is_non_clock_global="true"/>
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<output name="clkout" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
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<fc_override port_name="clkin_ext" fc_type="frac" fc_val="0"/>
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</fc>
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<pinlocations pattern="custom">
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<loc side="left">ckbuf_right.clkin_int ckbuf_right.clkin_ext ckbuf_right.clkout</loc>
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</pinlocations>
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</tile>
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<!-- CLB has most pins on the top and right sides -->
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@ -205,7 +277,10 @@
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<col type="io_left" startx="0" priority="100"/>
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<col type="io_right" startx="W-1" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<single type="ckbuf_bot" x="H/2" y="0" priority="20"/>
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<single type="ckbuf_bottom" x="W/2" y="0" priority="120"/>
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<single type="ckbuf_top" x="W/2" y="H-1" priority="120"/>
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<single type="ckbuf_left" x="0" y="H/2" priority="120"/>
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<single type="ckbuf_right" x="W-1" y="H/2" priority="120"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</fixed_layout>
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@ -341,42 +416,83 @@
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<!-- Define I/O pads ends -->
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<!-- Define clock buffers begin -->
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<pb_type name="ckbuf">
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<input name="clkin" num_pins="1"/>
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<input name="clkin_int" num_pins="1"/>
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<input name="clkin_ext" num_pins="1"/>
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<output name="clkout" num_pins="1"/>
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<!-- A mode denotes the physical implementation of an I/O
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This mode will be not packable but is mainly used for fabric verilog generation
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-->
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<mode name="physical" disabled_in_pack="true">
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<pb_type name="BUF" blif_model=".subckt ckbuf" num_pb="1">
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<pb_type name="ck_buff" blif_model=".subckt ck_buff" num_pb="1">
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<input name="in" num_pins="1"/>
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<output name="out" num_pins="1"/>
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<delay_matrix type="max" in_port="ck_buff.in" out_port="ck_buff.out">
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261e-12
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</delay_matrix>
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</pb_type>
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<interconnect>
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<direct name="in" input="ckbuf.clkin" output="BUF.in">
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<direct name="out" input="BUF.out" output="ckbuf.clkout">
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<mux name="mux2" input="ckbuf.clkin_int ckbuf.clkin_ext" output="ck_buff.in"/>
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<!--direct name="in" input="ckbuf.clkin_int" output="ck_buff.in">
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<delay_constant max="4.243e-11" in_port="ckbuf.clkin_int" out_port="ck_buff.in"/>
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</direct>
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<direct name="ded_in" input="ckbuf.clkin_ext" output="ck_buff.ded_in">
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<delay_constant max="4.243e-11" in_port="ckbuf.clkin_ext" out_port="ck_buff.ded_in"/>
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</direct -->
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<direct name="out" input="ck_buff.out" output="ckbuf.clkout">
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<delay_constant max="4.243e-11" in_port="ck_buff.out" out_port="ckbuf.clkout"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="default">
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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<mode name="internal">
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<pb_type name="CKBUFFINT" blif_model=".subckt ck_buff_int" num_pb="1">
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<output name="out" num_pins="1"/>
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<input name="in" num_pins="1"/>
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<delay_matrix type="max" in_port="CKBUFFINT.in" out_port="CKBUFFINT.out">
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261e-12
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</delay_matrix>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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<direct name="CLKIN" input="ckbuf.clkin_int" output="CKBUFFINT.in">
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<delay_constant max="4.243e-11" in_port="ckbuf.clkin_int" out_port="CKBUFFINT.in"/>
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</direct>
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<direct name="CLKOUT" output="ckbuf.clkout" input="CKBUFFINT.out">
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<delay_constant max="4.243e-11" in_port="CKBUFFINT.out" out_port="ckbuf.clkout"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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<mode name="external">
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<pb_type name="CKPAD" blif_model=".subckt ck_buff" num_pb="1">
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<output name="out" num_pins="1"/>
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<input name="in" num_pins="1"/>
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<delay_matrix type="max" in_port="CKPAD.in" out_port="CKPAD.out">
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261e-12
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</delay_matrix>
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</pb_type>
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<pb_type name="CKBUFF" blif_model=".subckt ck_buff_int" num_pb="1">
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<output name="out" num_pins="1"/>
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<input name="in" num_pins="1"/>
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<delay_matrix type="max" in_port="CKBUFF.in" out_port="CKBUFF.out">
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261e-12
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</delay_matrix>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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<direct name="CLKIN" input="ckbuf.clkin_ext" output="CKPAD.in">
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<delay_constant max="4.243e-11" in_port="ckbuf.clkin_ext" out_port="CKPAD.in"/>
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</direct>
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<direct name="CLKOUT" output="ckbuf.clkout" input="CKBUFF.out">
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<delay_constant max="4.243e-11" in_port="CKBUFF.out" out_port="ckbuf.clkout"/>
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</direct>
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<direct name="direct1" input="CKPAD.out" output="CKBUFF.in">
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<delay_constant max="4.243e-11" in_port="CKPAD.out" out_port="CKBUFF.in"/>
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<pack_pattern name="ckbuf" in_port="CKPAD.out" out_port="CKBUFF.in"/>
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</direct>
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</interconnect>
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</mode>
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<interconnect>
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<mux name="mux2" input="ckbuf.clkin_int ckbuf.clkin_ext" output="ckbuf.clkout"/>
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</interconnect>
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<power method="ignore"/>
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</pb_type>
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<!-- Define I/O pads ends -->
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@ -528,13 +644,43 @@
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261e-12
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</delay_matrix>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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<!-- Define flip-flop -->
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<pb_type name="ff" num_pb="1">
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<input name="D" num_pins="1"/>
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<output name="Q" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<mode name="VPR_FF">
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<pb_type name="VPR_FF" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="VPR_FF.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="VPR_FF.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct input="VPR_FF.Q" name="FF-Q" output="ff.Q"/>
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<direct input="ff.D" name="VPR_FF-D" output="VPR_FF.D">
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<!--pack_pattern in_port="ff.D" name="LUT+FFA" out_port="VPR_FF.D"/ -->
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</direct>
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<direct input="ff.clk" name="VPR_FF-clk" output="VPR_FF.clk"/>
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</interconnect>
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</mode>
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<mode name="DFF">
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<pb_type name="DFF" blif_model=".subckt openfpga_ff" num_pb="1">
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<input name="D" num_pins="1"/>
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<output name="Q" num_pins="1"/>
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<clock name="C" num_pins="1"/>
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<T_setup value="66e-12" port="DFF.D" clock="C"/>
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<T_clock_to_Q max="124e-12" port="DFF.Q" clock="C"/>
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</pb_type>
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<interconnect>
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<direct input="DFF.Q" name="FF-Q" output="ff.Q"/>
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<direct input="ff.D" name="DFF-D" output="DFF.D">
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<!-- pack_pattern in_port="ff.D" name="LUT+FFB" out_port="DFF.D"/-->
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</direct>
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<direct input="ff.clk" name="DFF-clk" output="DFF.C"/>
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</interconnect>
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</mode>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
|
|||
|
||||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
# to debug use --verbose options
|
||||
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
|
||||
#link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
|
||||
link_openfpga_arch --sort_gsb_chan_node_in_edges
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
||||
|
|
@ -30,7 +31,8 @@ lut_truth_table_fixup
|
|||
# Build the module graph
|
||||
# - Enabled compression on routing architecture modules
|
||||
# - Enable pin duplication on grid modules
|
||||
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
|
||||
#build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
|
||||
build_fabric --compress_routing --duplicate_grid_pin --generate_random_fabric_key #--verbose
|
||||
|
||||
# Repack the netlist to physical pbs
|
||||
# This must be done before bitstream generator and testbench generation
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
As the FPGA core does not share the clock with Caravel SoC
|
||||
the actual clock frequency could be higher
|
||||
-->
|
||||
<operating frequency="50e6" num_cycles="auto" slack="0.2"/>
|
||||
<operating frequency="50e6" num_cycles="10000" slack="0.2"/>
|
||||
<!-- Use 50MHz as the Caravel SoC can operate at 50MHz
|
||||
As the FPGA core does not share the clock with Caravel SoC
|
||||
the actual programming clock frequency could be higher
|
||||
|
|
|
|||
Loading…
Reference in New Issue