diff --git a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
index aee247d..6712fdd 100644
--- a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -195,7 +195,7 @@
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diff --git a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index 6dc7cad..f266cd4 100644
--- a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
index 9143a86..4d14aac 100644
--- a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
+++ b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
@@ -16,7 +16,8 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
-link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+#link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+link_openfpga_arch --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
@@ -30,7 +31,8 @@ lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
-build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
+#build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
+build_fabric --compress_routing --duplicate_grid_pin --generate_random_fabric_key #--verbose
# Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation
diff --git a/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml b/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
index 92cf793..aca6f10 100644
--- a/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+++ b/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
@@ -11,7 +11,7 @@
As the FPGA core does not share the clock with Caravel SoC
the actual clock frequency could be higher
-->
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