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further changes to add 4 clock buffer tiles

This commit is contained in:
Tarachand Pagarani 2021-02-01 04:32:22 -08:00
parent 0b855869bc
commit dec0a0e160
4 changed files with 214 additions and 31 deletions
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41
ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
View File

@ -195,7 +195,7 @@
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/> <port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/> <port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/sky130_fd_sc_hd_wrapper.v"> <circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" is_default="true" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/sky130_fd_sc_hd_wrapper.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
@ -205,6 +205,14 @@
<port type="input" prefix="cin" lib_name="S" size="1"/> <port type="input" prefix="cin" lib_name="S" size="1"/>
<port type="output" prefix="cout" lib_name="X" size="1"/> <port type="output" prefix="cout" lib_name="X" size="1"/>
</circuit_model> </circuit_model>
<circuit_model type="hard_logic" name="ckbuff_wrapper" prefix="ckbuff_wrapper" verilog_netlist="/home/tpagarani/SOFA/HDL/common/ckbuff_wrapper.v">
<design_technology type="cmos"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
</circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" num_regions="1"/> <organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" num_regions="1"/>
@ -228,8 +236,20 @@
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/> <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection> </direct_connection>
<tile_annotations> <tile_annotations>
<global_port name="clk" is_clock="true" default_val="0"> <!--global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk[0:3]" x="-1" y="-1"/> <tile name="clb" port="clk[0:3]" x="-1" y="-1"/>
</global_port-->
<global_port name="clk[0]" default_val="0">
<tile name="ckbuf_bottom" port="clkin_ext" x="-1" y="-1"/>
</global_port>
<global_port name="clk[1]" default_val="0">
<tile name="ckbuf_right" port="clkin_ext" x="-1" y="-1"/>
</global_port>
<global_port name="clk[2]" default_val="0">
<tile name="ckbuf_left" port="clkin_ext" x="-1" y="-1"/>
</global_port>
<global_port name="clk[3]" default_val="0">
<tile name="ckbuf_top" port="clkin_ext" x="-1" y="-1"/>
</global_port> </global_port>
<global_port name="Reset" is_reset="true" default_val="1"> <global_port name="Reset" is_reset="true" default_val="1">
<tile name="clb" port="reset" x="-1" y="-1"/> <tile name="clb" port="reset" x="-1" y="-1"/>
@ -244,6 +264,16 @@
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block ckbuf -->
<pb_type name="ckbuf" physical_mode_name="physical" idle_mode_name="default"/>
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
<pb_type name="ckbuf[physical].ck_buff" circuit_model_name="ckbuff_wrapper"/>
<pb_type name="ckbuf[external].CKBUFF" physical_pb_type_name="ckbuf[physical].ck_buff"/>
<pb_type name="ckbuf[internal].CKBUFFINT" physical_pb_type_name="ckbuf[physical].ck_buff"/>
<pb_type name="ckbuf[external].CKPAD" physical_pb_type_name="ckbuf[physical].ck_buff"/>
<!-- End physical pb_type binding in complex block ckbuf -->
<!-- physical pb_type binding in complex block CLB --> <!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified --> <!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/> <pb_type name="clb.fle" physical_mode_name="physical"/>
@ -257,7 +287,12 @@
<port name="in" physical_mode_port="in[0:3]"/> <port name="in" physical_mode_port="in[0:3]"/>
<port name="out" physical_mode_port="lut4_out"/> <port name="out" physical_mode_port="lut4_out"/>
</pb_type> </pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/> <pb_type name="clb.fle[n1_lut4].ble4.ff[VPR_FF].VPR_FF" physical_pb_type_name="clb.fle[physical].fabric.ff">
<port name="C" physical_mode_port="clk"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.ff[DFF].DFF" physical_pb_type_name="clb.fle[physical].fabric.ff">
<port name="C" physical_mode_port="clk"/>
</pb_type>
<!-- Binding operating pb_types in mode 'shift_register' --> <!-- Binding operating pb_types in mode 'shift_register' -->
<pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/> <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
<!-- End physical pb_type binding in complex block IO --> <!-- End physical pb_type binding in complex block IO -->

188
ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -33,7 +33,25 @@
<port name="inpad"/> <port name="inpad"/>
</output_ports> </output_ports>
</model> </model>
<model name="ck_buff">
<input_ports>
<port name="in" combinational_sink_ports="out"/>
<!--port name="in"/-->
</input_ports>
<output_ports>
<port name="out"/>
</output_ports>
</model>
<model name="ck_buff_int">
<input_ports>
<port name="in" combinational_sink_ports="out"/>
<!--port name="in"/-->
</input_ports>
<output_ports>
<port name="out"/>
</output_ports>
</model>
<model name="frac_lut4"> <model name="frac_lut4">
<input_ports> <input_ports>
<port name="in"/> <port name="in"/>
@ -65,6 +83,15 @@
<port name="Q" clock="clk"/> <port name="Q" clock="clk"/>
</output_ports> </output_ports>
</model> </model>
<model name="openfpga_ff">
<input_ports>
<port name="D" clock="C"/>
<port name="C" is_clock="1"/>
</input_ports>
<output_ports>
<port name="Q" clock="C"/>
</output_ports>
</model>
</models> </models>
<tiles> <tiles>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
@ -123,11 +150,56 @@
<equivalent_sites> <equivalent_sites>
<site pb_type="ckbuf"/> <site pb_type="ckbuf"/>
</equivalent_sites> </equivalent_sites>
<input name="clkin" num_pins="1"/> <input name="clkin_int" num_pins="1"/>
<input name="clkin_ext" num_pins="1" is_non_clock_global="true"/>
<output name="clkout" num_pins="1"/> <output name="clkout" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/> <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clkin_ext" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom"> <pinlocations pattern="custom">
<loc side="top">ckbuf.clkin ckbuf.clkout</loc> <loc side="top">ckbuf_bottom.clkin_int ckbuf_bottom.clkin_ext ckbuf_bottom.clkout</loc>
</pinlocations>
</tile>
<tile name="ckbuf_top" capacity="1" area="0">
<equivalent_sites>
<site pb_type="ckbuf"/>
</equivalent_sites>
<input name="clkin_int" num_pins="1"/>
<input name="clkin_ext" num_pins="1" is_non_clock_global="true"/>
<output name="clkout" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clkin_ext" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom">
<loc side="bottom">ckbuf_top.clkin_int ckbuf_top.clkin_ext ckbuf_top.clkout</loc>
</pinlocations>
</tile>
<tile name="ckbuf_left" capacity="1" area="0">
<equivalent_sites>
<site pb_type="ckbuf"/>
</equivalent_sites>
<input name="clkin_int" num_pins="1"/>
<input name="clkin_ext" num_pins="1" is_non_clock_global="true"/>
<output name="clkout" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clkin_ext" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom">
<loc side="right">ckbuf_left.clkin_int ckbuf_left.clkin_ext ckbuf_left.clkout</loc>
</pinlocations>
</tile>
<tile name="ckbuf_right" capacity="1" area="0">
<equivalent_sites>
<site pb_type="ckbuf"/>
</equivalent_sites>
<input name="clkin_int" num_pins="1"/>
<input name="clkin_ext" num_pins="1" is_non_clock_global="true"/>
<output name="clkout" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clkin_ext" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom">
<loc side="left">ckbuf_right.clkin_int ckbuf_right.clkin_ext ckbuf_right.clkout</loc>
</pinlocations> </pinlocations>
</tile> </tile>
<!-- CLB has most pins on the top and right sides --> <!-- CLB has most pins on the top and right sides -->
@ -205,7 +277,10 @@
<col type="io_left" startx="0" priority="100"/> <col type="io_left" startx="0" priority="100"/>
<col type="io_right" startx="W-1" priority="100"/> <col type="io_right" startx="W-1" priority="100"/>
<corners type="EMPTY" priority="101"/> <corners type="EMPTY" priority="101"/>
<single type="ckbuf_bot" x="H/2" y="0" priority="20"/> <single type="ckbuf_bottom" x="W/2" y="0" priority="120"/>
<single type="ckbuf_top" x="W/2" y="H-1" priority="120"/>
<single type="ckbuf_left" x="0" y="H/2" priority="120"/>
<single type="ckbuf_right" x="W-1" y="H/2" priority="120"/>
<!--Fill with 'clb'--> <!--Fill with 'clb'-->
<fill type="clb" priority="10"/> <fill type="clb" priority="10"/>
</fixed_layout> </fixed_layout>
@ -341,42 +416,83 @@
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define clock buffers begin --> <!-- Define clock buffers begin -->
<pb_type name="ckbuf"> <pb_type name="ckbuf">
<input name="clkin" num_pins="1"/> <input name="clkin_int" num_pins="1"/>
<input name="clkin_ext" num_pins="1"/>
<output name="clkout" num_pins="1"/> <output name="clkout" num_pins="1"/>
<!-- A mode denotes the physical implementation of an I/O <!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation This mode will be not packable but is mainly used for fabric verilog generation
--> -->
<mode name="physical" disabled_in_pack="true"> <mode name="physical" disabled_in_pack="true">
<pb_type name="BUF" blif_model=".subckt ckbuf" num_pb="1"> <pb_type name="ck_buff" blif_model=".subckt ck_buff" num_pb="1">
<input name="in" num_pins="1"/> <input name="in" num_pins="1"/>
<output name="out" num_pins="1"/> <output name="out" num_pins="1"/>
<delay_matrix type="max" in_port="ck_buff.in" out_port="ck_buff.out">
261e-12
</delay_matrix>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="in" input="ckbuf.clkin" output="BUF.in"> <mux name="mux2" input="ckbuf.clkin_int ckbuf.clkin_ext" output="ck_buff.in"/>
<direct name="out" input="BUF.out" output="ckbuf.clkout"> <!--direct name="in" input="ckbuf.clkin_int" output="ck_buff.in">
<delay_constant max="4.243e-11" in_port="ckbuf.clkin_int" out_port="ck_buff.in"/>
</direct>
<direct name="ded_in" input="ckbuf.clkin_ext" output="ck_buff.ded_in">
<delay_constant max="4.243e-11" in_port="ckbuf.clkin_ext" out_port="ck_buff.ded_in"/>
</direct -->
<direct name="out" input="ck_buff.out" output="ckbuf.clkout">
<delay_constant max="4.243e-11" in_port="ck_buff.out" out_port="ckbuf.clkout"/>
</direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="default"> <mode name="internal">
<pb_type name="inpad" blif_model=".input" num_pb="1"> <pb_type name="CKBUFFINT" blif_model=".subckt ck_buff_int" num_pb="1">
<output name="inpad" num_pins="1"/> <output name="out" num_pins="1"/>
<input name="in" num_pins="1"/>
<delay_matrix type="max" in_port="CKBUFFINT.in" out_port="CKBUFFINT.out">
261e-12
</delay_matrix>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad"> <direct name="CLKIN" input="ckbuf.clkin_int" output="CKBUFFINT.in">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/> <delay_constant max="4.243e-11" in_port="ckbuf.clkin_int" out_port="CKBUFFINT.in"/>
</direct>
<direct name="CLKOUT" output="ckbuf.clkout" input="CKBUFFINT.out">
<delay_constant max="4.243e-11" in_port="CKBUFFINT.out" out_port="ckbuf.clkout"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<mode name="outpad">
<pb_type name="outpad" blif_model=".output" num_pb="1"> <mode name="external">
<input name="outpad" num_pins="1"/> <pb_type name="CKPAD" blif_model=".subckt ck_buff" num_pb="1">
<output name="out" num_pins="1"/>
<input name="in" num_pins="1"/>
<delay_matrix type="max" in_port="CKPAD.in" out_port="CKPAD.out">
261e-12
</delay_matrix>
</pb_type>
<pb_type name="CKBUFF" blif_model=".subckt ck_buff_int" num_pb="1">
<output name="out" num_pins="1"/>
<input name="in" num_pins="1"/>
<delay_matrix type="max" in_port="CKBUFF.in" out_port="CKBUFF.out">
261e-12
</delay_matrix>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad"> <direct name="CLKIN" input="ckbuf.clkin_ext" output="CKPAD.in">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/> <delay_constant max="4.243e-11" in_port="ckbuf.clkin_ext" out_port="CKPAD.in"/>
</direct>
<direct name="CLKOUT" output="ckbuf.clkout" input="CKBUFF.out">
<delay_constant max="4.243e-11" in_port="CKBUFF.out" out_port="ckbuf.clkout"/>
</direct>
<direct name="direct1" input="CKPAD.out" output="CKBUFF.in">
<delay_constant max="4.243e-11" in_port="CKPAD.out" out_port="CKBUFF.in"/>
<pack_pattern name="ckbuf" in_port="CKPAD.out" out_port="CKBUFF.in"/>
</direct> </direct>
</interconnect> </interconnect>
</mode> </mode>
<interconnect>
<mux name="mux2" input="ckbuf.clkin_int ckbuf.clkin_ext" output="ckbuf.clkout"/>
</interconnect>
<power method="ignore"/> <power method="ignore"/>
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
@ -529,12 +645,42 @@
</delay_matrix> </delay_matrix>
</pb_type> </pb_type>
<!-- Define flip-flop --> <!-- Define flip-flop -->
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop"> <pb_type name="ff" num_pb="1">
<input name="D" num_pins="1"/>
<output name="Q" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<mode name="VPR_FF">
<pb_type name="VPR_FF" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/> <input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/> <output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/> <clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/> <T_setup value="66e-12" port="VPR_FF.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/> <T_clock_to_Q max="124e-12" port="VPR_FF.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct input="VPR_FF.Q" name="FF-Q" output="ff.Q"/>
<direct input="ff.D" name="VPR_FF-D" output="VPR_FF.D">
<!--pack_pattern in_port="ff.D" name="LUT+FFA" out_port="VPR_FF.D"/ -->
</direct>
<direct input="ff.clk" name="VPR_FF-clk" output="VPR_FF.clk"/>
</interconnect>
</mode>
<mode name="DFF">
<pb_type name="DFF" blif_model=".subckt openfpga_ff" num_pb="1">
<input name="D" num_pins="1"/>
<output name="Q" num_pins="1"/>
<clock name="C" num_pins="1"/>
<T_setup value="66e-12" port="DFF.D" clock="C"/>
<T_clock_to_Q max="124e-12" port="DFF.Q" clock="C"/>
</pb_type>
<interconnect>
<direct input="DFF.Q" name="FF-Q" output="ff.Q"/>
<direct input="ff.D" name="DFF-D" output="DFF.D">
<!-- pack_pattern in_port="ff.D" name="LUT+FFB" out_port="DFF.D"/-->
</direct>
<direct input="ff.clk" name="DFF-clk" output="DFF.C"/>
</interconnect>
</mode>
</pb_type> </pb_type>
<interconnect> <interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/> <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>

6
SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
View File

@ -16,7 +16,8 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base # Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options # to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges #link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
link_openfpga_arch --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist # Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
@ -30,7 +31,8 @@ lut_truth_table_fixup
# Build the module graph # Build the module graph
# - Enabled compression on routing architecture modules # - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules # - Enable pin duplication on grid modules
build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose #build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key ${EXTERNAL_FABRIC_KEY_FILE} #--verbose
build_fabric --compress_routing --duplicate_grid_pin --generate_random_fabric_key #--verbose
# Repack the netlist to physical pbs # Repack the netlist to physical pbs
# This must be done before bitstream generator and testbench generation # This must be done before bitstream generator and testbench generation

2
SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
View File

@ -11,7 +11,7 @@
As the FPGA core does not share the clock with Caravel SoC As the FPGA core does not share the clock with Caravel SoC
the actual clock frequency could be higher the actual clock frequency could be higher
--> -->
<operating frequency="50e6" num_cycles="auto" slack="0.2"/> <operating frequency="50e6" num_cycles="10000" slack="0.2"/>
<!-- Use 50MHz as the Caravel SoC can operate at 50MHz <!-- Use 50MHz as the Caravel SoC can operate at 50MHz
As the FPGA core does not share the clock with Caravel SoC As the FPGA core does not share the clock with Caravel SoC
the actual programming clock frequency could be higher the actual programming clock frequency could be higher