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[Script] Update report timing script for switch blocks in the purpose of one-shot report generation

This commit is contained in:
tangxifan 2021-04-01 18:04:56 -06:00
parent 7b49fa0684
commit db203b3690
1 changed files with 55 additions and 48 deletions
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103
SNPS_PT/SCRIPT/report_timing_sb.tcl
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@ -3,17 +3,22 @@
# using Synopsys PrimeTime # using Synopsys PrimeTime
##################################################################### #####################################################################
##################################
# Ensure a clean start
remove_design -all
remove_lib -all
################################## ##################################
# Define environment variables # Define environment variables
set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; #set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
set DEVICE_NAME "SOFA" set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
#set DEVICE_NAME "SOFA_HD"
set DEVICE_NAME "QLSOFA_HD"
#set DEVICE_NAME "SOFA_CHD"
set TIMING_REPORT_HOME "../TIMING_REPORTS/"; set TIMING_REPORT_HOME "../TIMING_REPORTS/";
# Enable preprocessing in Verilog parser # Enable preprocessing in Verilog parser
set_app_var svr_enable_vpp true set_app_var svr_enable_vpp true
@ -27,48 +32,50 @@ set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v" set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
################################## ##################################
# Read timing libraries # Sweep all the SB designs
read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db" set DESIGN_NAMES {"sb_1__1_" "sb_0__0_" "sb_0__2_" "sb_0__1_" "sb_2__0_" "sb_2__2_" "sb_2__1_" "sb_1__0_" "sb_1__2_"};
################################## foreach DESIGN_NAME ${DESIGN_NAMES} {
# Read post-PnR netlists
read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
# Top-level module name
#set DESIGN_NAME sb_1__1_;
#set DESIGN_NAME "sb_0__0_";
#set DESIGN_NAME "sb_0__2_";
#set DESIGN_NAME "sb_0__1_";
#set DESIGN_NAME "sb_2__0_";
#set DESIGN_NAME "sb_2__2_";
#set DESIGN_NAME "sb_2__1_";
#set DESIGN_NAME "sb_1__0_";
set DESIGN_NAME "sb_1__2_";
link_design ${DESIGN_NAME} ##################################
# Ensure a clean start
######################################### remove_design -all
# Setup constraints to break combinational loops remove_lib -all
set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
# ##################################
########################################## # Read timing libraries
## Setup constraints for clocks read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
########################################## ##################################
## Setup constraints for paths # Read post-PnR netlists
## Switch block name read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
set SB_CHAN_NAME "chan*";
set SB_PIN_NAME "*grid_pin*"; link_design ${DESIGN_NAME}
set_max_delay -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} 2.272500113e-12
set_max_delay -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} 7.247000222e-11 #########################################
# Setup constraints to break combinational loops
################################## set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
# Read post-PnR parasitics #
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef ##########################################
## Setup constraints for clocks
##################################
# Report timing of Connect block ##########################################
report_timing -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt ## Setup constraints for paths
report_timing -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt ## Switch block name
set SB_CHAN_NAME "chan*";
set SB_PIN_NAME "*grid_pin*";
set_max_delay -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} 2.272500113e-12
set_max_delay -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} 7.247000222e-11
##################################
# Read post-PnR parasitics
read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
##################################
# Report timing of Connect block
report_timing -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
report_timing -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
}
################################## ##################################
# Finish and quit # Finish and quit