diff --git a/SNPS_PT/SCRIPT/report_timing_sb.tcl b/SNPS_PT/SCRIPT/report_timing_sb.tcl
index 5a6c846..9e426b7 100644
--- a/SNPS_PT/SCRIPT/report_timing_sb.tcl
+++ b/SNPS_PT/SCRIPT/report_timing_sb.tcl
@@ -3,17 +3,22 @@
 # using Synopsys PrimeTime
 #####################################################################
  
-##################################
-# Ensure a clean start
-remove_design -all
-remove_lib -all
-
 ##################################
 # Define environment variables
 set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
-set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
-set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
-set DEVICE_NAME "SOFA"
+
+#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
+set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
+#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
+
+#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
+set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
+#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
+
+#set DEVICE_NAME "SOFA_HD"
+set DEVICE_NAME "QLSOFA_HD"
+#set DEVICE_NAME "SOFA_CHD"
+
 set TIMING_REPORT_HOME "../TIMING_REPORTS/";
 # Enable preprocessing in Verilog parser
 set_app_var svr_enable_vpp true
@@ -27,48 +32,50 @@ set link_path "* sky130_fd_sc_hd__tt_025C_1v80.db"
 set FPGA_NETLIST_FILES "fpga_top_icv_in_design.pt.v"
 
 ##################################
-# Read timing libraries
-read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
+# Sweep all the SB designs
+set DESIGN_NAMES {"sb_1__1_" "sb_0__0_" "sb_0__2_" "sb_0__1_" "sb_2__0_" "sb_2__2_" "sb_2__1_" "sb_1__0_" "sb_1__2_"};
 
-##################################
-# Read post-PnR netlists
-read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
-# Top-level module name
-#set DESIGN_NAME sb_1__1_;
-#set DESIGN_NAME "sb_0__0_";
-#set DESIGN_NAME "sb_0__2_";
-#set DESIGN_NAME "sb_0__1_";
-#set DESIGN_NAME "sb_2__0_";
-#set DESIGN_NAME "sb_2__2_";
-#set DESIGN_NAME "sb_2__1_";
-#set DESIGN_NAME "sb_1__0_";
-set DESIGN_NAME "sb_1__2_";
+foreach DESIGN_NAME ${DESIGN_NAMES} {
 
-link_design ${DESIGN_NAME}
-
-#########################################
-# Setup constraints to break combinational loops
-set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
-#
-##########################################
-## Setup constraints for clocks
-
-##########################################
-## Setup constraints for paths
-## Switch block name
-set SB_CHAN_NAME "chan*";
-set SB_PIN_NAME "*grid_pin*";
-set_max_delay -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} 2.272500113e-12
-set_max_delay -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} 7.247000222e-11
-
-##################################
-# Read post-PnR parasitics
-read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
-
-##################################
-# Report timing of Connect block
-report_timing -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
-report_timing -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
+  ##################################
+  # Ensure a clean start
+  remove_design -all
+  remove_lib -all
+  
+  ##################################
+  # Read timing libraries
+  read_db "${SKYWATER_PDK_HOME}/vendor/synopsys/PlaceRoute/sky130_fd_sc_hd/db_nldm/sky130_fd_sc_hd__tt_025C_1v80.db"
+  
+  ##################################
+  # Read post-PnR netlists
+  read_verilog ${FPGA_NETLIST_HOME}/${FPGA_NETLIST_FILES}
+  
+  link_design ${DESIGN_NAME}
+  
+  #########################################
+  # Setup constraints to break combinational loops
+  set_disable_timing mem*/sky*_fd_sc_hd__dfxtp_*_*_/D
+  #
+  ##########################################
+  ## Setup constraints for clocks
+  
+  ##########################################
+  ## Setup constraints for paths
+  ## Switch block name
+  set SB_CHAN_NAME "chan*";
+  set SB_PIN_NAME "*grid_pin*";
+  set_max_delay -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} 2.272500113e-12
+  set_max_delay -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} 7.247000222e-11
+  
+  ##################################
+  # Read post-PnR parasitics
+  read_parasitics ${FPGA_NETLIST_HOME}/fpga_top_icv_in_design.nominal_25.spef
+  
+  ##################################
+  # Report timing of Connect block
+  report_timing -from ${SB_CHAN_NAME} -to ${SB_CHAN_NAME} > ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
+  report_timing -from ${SB_PIN_NAME} -to ${SB_CHAN_NAME} >> ${TIMING_REPORT_HOME}/${DEVICE_NAME}_${DESIGN_NAME}_timing.rpt
+}
 
 ##################################
 # Finish and quit