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more updates to clock buffer representation

This commit is contained in:
Tarachand Pagarani 2021-02-02 09:52:18 -08:00
parent dec0a0e160 61655b8e1e
commit d757605989
6 changed files with 657 additions and 198 deletions
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229
ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -1,14 +1,14 @@
<!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block
- K = 6, N = 10, I = 40
- Single mode
- Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1
- Skywater 130nm PDK
- circuit models are binded to the opensource skywater
foundry middle-speed (ms) standard cell library
-->
This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block
- K = 6, N = 10, I = 40
- Single mode
- Routing architecture
- L = 4, fc_in = 0.15, fc_out = 0.1
- Skywater 130nm PDK
- circuit models are binded to the opensource skywater
foundry middle-speed (ms) standard cell library
-->
<openfpga_architecture>
<technology_library>
<device_library>
@ -43,6 +43,18 @@
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_1" prefix="sky130_fd_sc_hd__buf_1" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v">
<design_technology type="cmos" topology="buffer" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
<device_technology device_model_name="logic"/>
@ -67,6 +79,30 @@
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_8" prefix="sky130_fd_sc_hd__buf_8" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_16" prefix="sky130_fd_sc_hd__buf_16" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
<design_technology type="cmos" topology="buffer" size="1"/>
<device_technology device_model_name="logic"/>
@ -79,6 +115,35 @@
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_4" prefix="sky130_fd_sc_hd__inv_4" is_default="false" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v">
<design_technology type="cmos" topology="buffer" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<!-- Trick OpenFPGA to avoid auto-generating TGATE modules, which are not used in PnR -->
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/fd_hd_mux_custom_cells_tt.v">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="input" prefix="sel" size="1"/>
<port type="input" prefix="selb" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
10e-12 5e-12 5e-12
</delay_matrix>
</circuit_model>
<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
<design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/>
@ -129,6 +194,78 @@
<wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_1"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf4" prefix="mux_2level_tapbuf4" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf8" prefix="mux_2level_tapbuf8" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_8"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf16" prefix="mux_2level_tapbuf16" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_16"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level" prefix="mux_1level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="1" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_io" prefix="mux_1level_io" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="1" local_encoder="false"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_1"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_fabric" prefix="mux_1level_fabric" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="1" local_encoder="false"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_1"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi_level" num_level="1" add_const_input="true" const_input_val="1" local_encoder="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_4"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="false"/>
@ -147,7 +284,6 @@
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="sky130_fd_sc_hd__sdfrtp_1" prefix="sky130_fd_sc_hd__sdfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
@ -167,33 +303,50 @@
<lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
<lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
<port type="input" prefix="in" size="4"/>
<port type="output" prefix="lut2_out" size="2" lut_frac_level="2" lut_output_mask="2,3"/>
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
<port type="sram" prefix="sram" size="16"/>
<port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="sky130_fd_sc_hd__dfrtp_1" prefix="sky130_fd_sc_hd__dfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v">
<!-- new ccFF -->
<circuit_model type="ccff" name="QL_CCFF" prefix="QL_CCFF" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/ql_ccff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
<port type="input" prefix="Test_en" lib_name="SE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="CFG_DONE" lib_name="CFGE" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="SI" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="CFGQN" size="1"/>
<port type="output" prefix="CFGQ" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
</circuit_model>
<circuit_model type="iopad" name="EMBEDDED_IO_HD" prefix="EMBEDDED_IO_HD" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/digital_io_hd.v">
<!-- dummy stdcell pointer -->
<circuit_model type="inv_buf" name="dummy1" prefix="dummy1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_1.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="dummy2" prefix="dummy2" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_1.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="dummy3" prefix="dummy3" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/einvn/sky130_fd_sc_hd__einvn_4.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="dummy4" prefix="dummy4" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and3/sky130_fd_sc_hd__and3_1.v">
<design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model>
<circuit_model type="iopad" name="IO" prefix="IO" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/ql_iso_io_logic.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
<port type="input" prefix="A2F" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="F2A" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" default_val="1"/>
<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
<port type="input" prefix="CFG_DONE" lib_name="CFG_DONE" size="1" is_global="true" default_val="0"/>
<port type="sram" prefix="io_dir" lib_name="FPGA_IO_DIR" size="1" mode_select="true" circuit_model_name="QL_CCFF" default_val="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" is_default="true" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/sky130_fd_sc_hd_wrapper.v">
<design_technology type="cmos"/>
@ -215,7 +368,7 @@
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfrtp_1" num_regions="1"/>
<organization type="scan_chain" circuit_model_name="QL_CCFF" num_regions="1"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
@ -259,30 +412,46 @@
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
<pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<pb_type name="io[physical].iopad">
<interconnect name="mux1" circuit_model_name="mux_1level_io"/>
<interconnect name="mux2" circuit_model_name="mux_1level_io"/>
</pb_type>
<pb_type name="io[physical].iopad.pad" circuit_model_name="IO" mode_bits="1"/>
<pb_type name="io[io_input].io_input.inpad" physical_pb_type_name="io[physical].iopad.pad" mode_bits="1"/>
<pb_type name="io[io_output].io_output.outpad" physical_pb_type_name="io[physical].iopad.pad" mode_bits="0"/>
<pb_type name="io[physical].iopad.ff" circuit_model_name="sky130_fd_sc_hd__sdfrtp_1"/>
<pb_type name="io[io_input].io_input.ff" physical_pb_type_name="io[physical].iopad.ff"/>
<pb_type name="io[io_output].io_output.ff" physical_pb_type_name="io[physical].iopad.ff"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block ckbuf -->
<pb_type name="ckbuf" physical_mode_name="physical" idle_mode_name="default"/>
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
<pb_type name="ckbuf[physical].ck_buff" circuit_model_name="ckbuff_wrapper"/>
<pb_type name="ckbuf[physical].ck_pad" circuit_model_name="ckbuff_wrapper"/>
<pb_type name="ckbuf[external].CKBUFF" physical_pb_type_name="ckbuf[physical].ck_buff"/>
<pb_type name="ckbuf[internal].CKBUFFINT" physical_pb_type_name="ckbuf[physical].ck_buff"/>
<pb_type name="ckbuf[external].CKPAD" physical_pb_type_name="ckbuf[physical].ck_buff"/>
<pb_type name="ckbuf[external].CKPAD" physical_pb_type_name="ckbuf[physical].ck_pad"/>
<!-- End physical pb_type binding in complex block ckbuf -->
<!-- physical pb_type binding in complex block CLB -->
<pb_type name="clb.fle[physical].fabric">
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
<interconnect name="mux1" circuit_model_name="mux_1level_fabric"/>
<interconnect name="mux2" circuit_model_name="mux_1level_fabric"/>
</pb_type>
<pb_type name="clb.fle[physical].fabric.frac_logic">
<interconnect name="mux2" circuit_model_name="mux_1level_fabric"/>
</pb_type>
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.carry_follower" circuit_model_name="sky130_fd_sc_hd__mux2_1_wrapper"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfrtp_1"/>
<!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'ble4' -->
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4">
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:3]"/>
<port name="out" physical_mode_port="lut4_out"/>

272
ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -1,17 +1,17 @@
<!--
Low-cost homogeneous FPGA Architecture.
Low-cost homogeneous FPGA Architecture.
- Skywater 130 nm technology
- General purpose logic block:
K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared)
with optionally registered outputs
- Routing architecture:
- 10% L = 1, fc_in = 0.15, Fc_out = 0.10
- 10% L = 2, fc_in = 0.15, Fc_out = 0.10
- 80% L = 4, fc_in = 0.15, Fc_out = 0.10
- 100 routing tracks per channel
- Skywater 130 nm technology
- General purpose logic block:
K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared)
with optionally registered outputs
- Routing architecture:
- 10% L = 1, fc_in = 0.15, Fc_out = 0.10
- 10% L = 2, fc_in = 0.15, Fc_out = 0.10
- 80% L = 4, fc_in = 0.15, Fc_out = 0.10
- 100 routing tracks per channel
Authors: Xifan Tang
Authors: Xifan Tang
-->
<architecture>
<!--
@ -33,7 +33,7 @@
<port name="inpad"/>
</output_ports>
</model>
<model name="ck_buff">
<model name="ck_pad">
<input_ports>
<port name="in" combinational_sink_ports="out"/>
<!--port name="in"/-->
@ -43,7 +43,7 @@
</output_ports>
</model>
<model name="ck_buff_int">
<model name="ck_buff">
<input_ports>
<port name="in" combinational_sink_ports="out"/>
<!--port name="in"/-->
@ -103,11 +103,20 @@
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<clock name="clk" num_pins="4"/>
<input name="f2a_i" num_pins="1"/>
<output name="a2f_o" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom">
<loc side="bottom">io_top.outpad io_top.inpad</loc>
<loc side="bottom">io_top.a2f_o io_top.f2a_i io_top.clk io_top.sc_in io_top.sc_out io_top.reset</loc>
</pinlocations>
</tile>
<!-- Right-side has 1 I/O per tile -->
@ -115,11 +124,20 @@
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<clock name="clk" num_pins="4"/>
<input name="f2a_i" num_pins="1"/>
<output name="a2f_o" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom">
<loc side="left">io_right.outpad io_right.inpad</loc>
<loc side="left">io_right.a2f_o io_right.f2a_i io_right.clk io_right.sc_in io_right.sc_out io_right.reset</loc>
</pinlocations>
</tile>
<!-- Bottom-side has 9 I/O per tile -->
@ -127,11 +145,20 @@
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<clock name="clk" num_pins="4"/>
<input name="f2a_i" num_pins="1"/>
<output name="a2f_o" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom">
<loc side="top">io_bottom.outpad io_bottom.inpad</loc>
<loc side="top">io_bottom.a2f_o io_bottom.f2a_i io_bottom.clk io_bottom.sc_in io_bottom.sc_out io_bottom.reset</loc>
</pinlocations>
</tile>
<!-- Left-side has 1 I/O per tile -->
@ -139,11 +166,20 @@
<equivalent_sites>
<site pb_type="io"/>
</equivalent_sites>
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<clock name="clk" num_pins="4"/>
<input name="f2a_i" num_pins="1"/>
<output name="a2f_o" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_in" fc_type="frac" fc_val="0"/>
<fc_override port_name="sc_out" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="custom">
<loc side="right">io_left.outpad io_left.inpad</loc>
<loc side="right">io_left.a2f_o io_left.f2a_i io_left.clk io_left.sc_in io_left.sc_out io_left.reset</loc>
</pinlocations>
</tile>
<tile name="ckbuf_bottom" capacity="1" area="0">
@ -362,56 +398,123 @@
<complexblocklist>
<!-- Define input pads begin -->
<pb_type name="io">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
If you need to register the I/O, define clocks in the circuit models
These clocks can be handled in back-end
-->
<!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation
-->
<clock name="clk" num_pins="4"/>
<input name="f2a_i" num_pins="1"/>
<output name="a2f_o" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<!-- Physical mode definition begin (physical implementation of the io) -->
<mode name="physical" disabled_in_pack="true">
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
<pb_type name="iopad" num_pb="1">
<clock name="clk" num_pins="1"/>
<input name="f2a_i" num_pins="1"/>
<output name="a2f_o" num_pins="1"/>
<input name="sc_in" num_pins="1"/>
<input name="reset" num_pins="1"/>
<output name="sc_out" num_pins="1"/>
<pb_type name="ff" blif_model=".subckt scff" num_pb="2">
<input name="D" num_pins="1" port_class="D"/>
<input name="DI" num_pins="1"/>
<input name="reset" num_pins="1"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_setup value="66e-12" port="ff.DI" clock="clk"/>
<T_setup value="66e-12" port="ff.reset" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<pb_type name="pad" blif_model=".subckt io" num_pb="1">
<input name="outpad" num_pins="1"/>
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="iopad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
</direct>
<direct name="inpad" input="iopad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
</direct>
<direct name="ff[0:0]-clk" input="iopad.clk" output="ff[0:0].clk"/>
<direct name="ff[1:1]-clk" input="iopad.clk" output="ff[1:1].clk"/>
<direct name="ff[0:0]-D" input="iopad.f2a_i" output="ff[0:0].D" />
<direct name="ff[1:1]-D" input="pad.inpad" output="ff[1:1].D"/>
<direct name="ff[0:0]-DI" input="iopad.sc_in" output="ff[0:0].DI"/>
<direct name="ff[1:1]-DI" input="ff[0:0].Q" output="ff[1:1].DI"/>
<direct name="iopad-sc_out" input="ff[1:1].Q" output="iopad.sc_out"/>
<complete name="complete1" input="iopad.reset" output="ff[1:0].reset"/>
<mux name="mux1" input="iopad.f2a_i ff[0:0].Q" output="pad.outpad">
<delay_constant max="25e-12" in_port="iopad.f2a_i" out_port="pad.outpad"/>
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="pad.outpad"/>
</mux>
<mux name="mux2" input="pad.inpad ff[1:1].Q" output="iopad.a2f_o">
<delay_constant max="25e-12" in_port="pad.inpad" out_port="iopad.a2f_o"/>
<delay_constant max="45e-12" in_port="ff[1:1].Q" out_port="iopad.a2f_o"/>
</mux>
</interconnect>
</mode>
<!-- IOs can operate as either inputs or outputs.
Delays below come from Ian Kuon. They are small, so they should be interpreted as
the delays to and from registers in the I/O (and generally I/Os are registered
today and that is when you timing analyze them.
-->
<mode name="inpad">
<pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="inpad" input="inpad.inpad" output="io.inpad">
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
</direct>
<complete name="clks" input="io.clk" output="iopad.clk"/>
<direct name="direct3" input="io.f2a_i" output="iopad.f2a_i"/>
<direct name="direct4" input="iopad.a2f_o" output="io.a2f_o"/>
<direct name="direct6" input="io.sc_in" output="iopad.sc_in"/>
<direct name="direct7" input="iopad.sc_out" output="io.sc_out"/>
<direct name="direct8" input="io.reset" output="iopad.reset"/>
</interconnect>
</mode>
<mode name="outpad">
<!-- Physical mode definition end (physical implementation of the io) -->
<mode name="io_output">
<pb_type name="io_output" num_pb="1">
<clock name="clk" num_pins="1"/>
<input name="f2a_i" num_pins="1"/>
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<pb_type name="outpad" blif_model=".output" num_pb="1">
<input name="outpad" num_pins="1"/>
</pb_type>
<interconnect>
<direct name="outpad" input="io.outpad" output="outpad.outpad">
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
</direct>
<direct name="ff-clk" input="io_output.clk" output="ff.clk"/>
<direct name="ff-D" input="io_output.f2a_i" output="ff.D"/>
<mux name="mux1" input="ff.Q io_output.f2a_i" output="outpad.outpad">
<pack_pattern name="pack-OREG" in_port="ff.Q" out_port="outpad.outpad"/>
<delay_constant max="25e-12" in_port="io_output.f2a_i" out_port="outpad.outpad"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="outpad.outpad"/>
</mux>
</interconnect>
</pb_type>
<interconnect>
<complete name="io_output-clk" input="io.clk" output="io_output.clk"/>
<direct name="io_output-f2a_i" input="io.f2a_i" output="io_output.f2a_i"/>
</interconnect>
</mode>
<mode name="io_input">
<pb_type name="io_input" num_pb="1">
<clock name="clk" num_pins="1"/>
<output name="a2f_o" num_pins="1"/>
<pb_type name="inpad" blif_model=".input" num_pb="1">
<output name="inpad" num_pins="1"/>
</pb_type>
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="ff-clk" input="io_input.clk" output="ff.clk"/>
<direct name="ff-D" input="inpad.inpad" output="ff.D"/>
<mux name="mux2" input="inpad.inpad ff.Q" output="io_input.a2f_o">
<pack_pattern name="pack-IREG" in_port="ff.Q" out_port="io_input.a2f_o"/>
<delay_constant max="25e-12" in_port="inpad.inpad" out_port="io_input.a2f_o"/>
<delay_constant max="45e-12" in_port="ff.Q" out_port="io_input.a2f_o"/>
</mux>
</interconnect>
</pb_type>
<interconnect>
<direct name="io-a2f_o" input="io_input.a2f_o" output="io.a2f_o"/>
<complete name="io_input-clk" input="io.clk" output="io_input.clk"/>
</interconnect>
</mode>
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
<!-- Define clock buffers begin -->
@ -422,7 +525,14 @@
<!-- A mode denotes the physical implementation of an I/O
This mode will be not packable but is mainly used for fabric verilog generation
-->
<mode name="physical" disabled_in_pack="true">
<mode name="physical" disabled_in_pack="true" disable_packing="true">
<pb_type name="ck_pad" blif_model=".subckt ck_pad" num_pb="1">
<input name="in" num_pins="1"/>
<output name="out" num_pins="1"/>
<delay_matrix type="max" in_port="ck_pad.in" out_port="ck_pad.out">
261e-12
</delay_matrix>
</pb_type>
<pb_type name="ck_buff" blif_model=".subckt ck_buff" num_pb="1">
<input name="in" num_pins="1"/>
<output name="out" num_pins="1"/>
@ -431,13 +541,13 @@
</delay_matrix>
</pb_type>
<interconnect>
<mux name="mux2" input="ckbuf.clkin_int ckbuf.clkin_ext" output="ck_buff.in"/>
<!--direct name="in" input="ckbuf.clkin_int" output="ck_buff.in">
<mux name="mux2" input="ck_pad.out ckbuf.clkin_int" output="ck_buff.in"/>
<!-- direct name="in" input="ckbuf.clkin_int" output="ck_buff.in">
<delay_constant max="4.243e-11" in_port="ckbuf.clkin_int" out_port="ck_buff.in"/>
</direct-->
<direct name="ded_in" input="ckbuf.clkin_ext" output="ck_pad.in">
<delay_constant max="4.243e-11" in_port="ckbuf.clkin_ext" out_port="ck_pad.in"/>
</direct>
<direct name="ded_in" input="ckbuf.clkin_ext" output="ck_buff.ded_in">
<delay_constant max="4.243e-11" in_port="ckbuf.clkin_ext" out_port="ck_buff.ded_in"/>
</direct -->
<direct name="out" input="ck_buff.out" output="ckbuf.clkout">
<delay_constant max="4.243e-11" in_port="ck_buff.out" out_port="ckbuf.clkout"/>
</direct>
@ -445,7 +555,7 @@
</mode>
<mode name="internal">
<pb_type name="CKBUFFINT" blif_model=".subckt ck_buff_int" num_pb="1">
<pb_type name="CKBUFFINT" blif_model=".subckt ck_buff" num_pb="1">
<output name="out" num_pins="1"/>
<input name="in" num_pins="1"/>
<delay_matrix type="max" in_port="CKBUFFINT.in" out_port="CKBUFFINT.out">
@ -453,9 +563,10 @@
</delay_matrix>
</pb_type>
<interconnect>
<direct name="CLKIN" input="ckbuf.clkin_int" output="CKBUFFINT.in">
<mux name="CLKIN" input="ckbuf.clkin_int ckbuf.clkin_ext" output="CKBUFFINT.in">
<delay_constant max="4.243e-11" in_port="ckbuf.clkin_int" out_port="CKBUFFINT.in"/>
</direct>
<delay_constant max="4.243e-11" in_port="ckbuf.clkin_ext" out_port="CKBUFFINT.in"/>
</mux>
<direct name="CLKOUT" output="ckbuf.clkout" input="CKBUFFINT.out">
<delay_constant max="4.243e-11" in_port="CKBUFFINT.out" out_port="ckbuf.clkout"/>
</direct>
@ -463,14 +574,14 @@
</mode>
<mode name="external">
<pb_type name="CKPAD" blif_model=".subckt ck_buff" num_pb="1">
<pb_type name="CKPAD" blif_model=".subckt ck_pad" num_pb="1">
<output name="out" num_pins="1"/>
<input name="in" num_pins="1"/>
<delay_matrix type="max" in_port="CKPAD.in" out_port="CKPAD.out">
261e-12
</delay_matrix>
</pb_type>
<pb_type name="CKBUFF" blif_model=".subckt ck_buff_int" num_pb="1">
<pb_type name="CKBUFF" blif_model=".subckt ck_buff" num_pb="1">
<output name="out" num_pins="1"/>
<input name="in" num_pins="1"/>
<delay_matrix type="max" in_port="CKBUFF.in" out_port="CKBUFF.out">
@ -484,15 +595,16 @@
<direct name="CLKOUT" output="ckbuf.clkout" input="CKBUFF.out">
<delay_constant max="4.243e-11" in_port="CKBUFF.out" out_port="ckbuf.clkout"/>
</direct>
<direct name="direct1" input="CKPAD.out" output="CKBUFF.in">
<mux name="mux2" input="CKPAD.out ckbuf.clkin_int" output="CKBUFF.in">
<delay_constant max="4.243e-11" in_port="CKPAD.out" out_port="CKBUFF.in"/>
<delay_constant max="4.243e-11" in_port="ckbuf.clkin_int" out_port="CKBUFF.in"/>
<pack_pattern name="ckbuf" in_port="CKPAD.out" out_port="CKBUFF.in"/>
</direct>
</mux>
</interconnect>
</mode>
<interconnect>
<!--interconnect>
<mux name="mux2" input="ckbuf.clkin_int ckbuf.clkin_ext" output="ckbuf.clkout"/>
</interconnect>
</interconnect-->
<power method="ignore"/>
</pb_type>
<!-- Define I/O pads ends -->
@ -566,7 +678,6 @@
<direct name="direct4" input="frac_lut4.lut2_out[1:1]" output="carry_follower.a"/>
<direct name="direct5" input="frac_lut4.lut2_out[0:0]" output="carry_follower.cin"/>
<direct name="direct6" input="carry_follower.cout" output="frac_logic.cout"/>
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
<direct name="direct7" input="frac_lut4.lut4_out" output="frac_logic.out"/>
<mux name="mux2" input="frac_logic.cin frac_logic.in[2:2]" output="frac_lut4.in[2:2]"/>
</interconnect>
@ -760,13 +871,10 @@
<direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
<!-- Put all inter-block carry chain delay on this one edge -->
<delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
<!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
</direct>
<direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
<!--pack_pattern name="chain" in_port="fle[7:7].reg_out" out_port="clb.reg_out"/-->
</direct>
<direct name="shift_register_link" input="fle[6:0].reg_out" output="fle[7:1].reg_in">
<!--pack_pattern name="chain" in_port="fle[6:0].reg_out" out_port="fle[7:1].reg_in"/-->
</direct>
<!-- Scan chain links -->
<direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">

44
HDL/common/ql_ccff.v Normal file
View File

@ -0,0 +1,44 @@
`timescale 1ns/1ps
//-----------------------------------------------------
// Function : QuickLogic physical CCFF
// - intorduce CFGE to gate CCFF output for
// un-wanted toggling during configuration
// - intorduce test data in, SI, for DFM
//
// Note: This cell is built with Standard Cells from HD library
// It is already technology mapped and can be directly used
// for physical design
//-----------------------------------------------------
module QL_CCFF (
input RESET_B,
input SE,
input CFGE,
input D,
input SI,
output Q,
output CFGQN,
output CFGQ,
input CLK
);
sky130_fd_sc_hd__nand2_1 NAND2_CFGQN (
.A(Q),
.B(CFGE),
.X(CFGQN)
);
sky130_fd_sc_hd__inv_1 INV_CFGQN (
.A(CFGQN),
.Y(CFGQ)
);
sky130_fd_sc_hd__sdfrtp_1 SDFRTP (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SI),
.SCE(SE),
.RESET_B(RESET_B)
);
endmodule

52
HDL/common/ql_io_logic.v Normal file
View File

@ -0,0 +1,52 @@
`timescale 1ns/1ps
//-----------------------------------------------------
// Function : An embedded I/O with
// - An I/O isolation signal to set
// the I/O in input mode. This is to avoid
// any unexpected output signals to damage
// circuits outside the FPGA due to configurable
// memories are not properly initialized
// This feature may not be needed if the configurable
// memory cell has a built-in set/reset functionality
// - Internal protection circuitry to ensure
// clean signals at all the SOC I/O ports
// This is to avoid
// - output any random signal
// when the I/O is in input mode, also avoid
// - driven by any random signal
// when the I/O is output mode
//
// Note: This cell is built with Standard Cells from HD library
// It is already technology mapped and can be directly used
// for physical design
//-----------------------------------------------------
module EMBEDDED_IO_HD (
input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
input FPGA_IO_DIR,
input CFG_DONE
);
wire cfg_done_b;
sky130_fd_sc_hd__inv_1 INV (
.A(CFG_DONE),
.Y(cfg_done_b)
);
sky130_fd_sc_hd__or3_1 OR3 (
.A(FPGA_IO_DIR),
.B(FPGA_OUT),
.C(cfg_done_b),
.X(SOC_OUT)
);
sky130_fd_sc_hd__and2_1 AND2 (
.A(FPGA_IO_DIR),
.B(SOC_IN),
.X(FPGA_IN)
);
endmodule

70
HDL/common/ql_iso_io_logic.v Normal file
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@ -0,0 +1,70 @@
`timescale 1ns/1ps
//-----------------------------------------------------
// Function : An embedded I/O with
// - An I/O isolation signal to set
// the I/O in input mode. This is to avoid
// any unexpected output signals to damage
// circuits outside the FPGA due to configurable
// memories are not properly initialized
// This feature may not be needed if the configurable
// memory cell has a built-in set/reset functionality
// - Internal protection circuitry to ensure
// clean signals at all the SOC I/O ports
// This is to avoid
// - output any random signal
// when the I/O is in input mode, also avoid
// - driven by any random signal
// when the I/O is output mode
//
// Note: This cell is built with Standard Cells from HD library
// It is already technology mapped and can be directly used
// for physical design
//-----------------------------------------------------
module IO (
input SOC_IN, // Input to drive the inpad signal
output SOC_OUT, // Output the outpad signal
output FPGA_IN, // Input data to FPGA
input FPGA_OUT, // Output data from FPGA
input FPGA_IO_DIR,
input CFG_DONE,
input IO_ISOL_N
);
wire cfg_done_b;
wire io_isol;
wire f2a_o_gate;
wire f2a_o_int;
sky130_fd_sc_hd__inv_1 INV_CFG_DONE (
.A(CFG_DONE),
.Y(cfg_done_b)
);
sky130_fd_sc_hd__inv_1 INV_ISOL_N (
.A(IO_ISOL_N),
.Y(io_isol)
);
// output path
sky130_fd_sc_hd__nor2_1 NOR2 (
.A(FPGA_IO_DIR),
.B(cfg_done_b),
.Y(f2a_o_gate)
);
sky130_fd_sc_hd__nand2_1 NAND2 (
.A(FPGA_OUT),
.B(f2a_o_gate),
.Y(f2a_o_int)
);
sky130_fd_sc_hd__einvn_4 EINVN_OUT (
.A(f2a_o_int),
.TE_B(io_isol),
.Z(SOC_OUT)
);
// input path
sky130_fd_sc_hd__and3_1 AND3 (
.A(SOC_IN),
.B(FPGA_IO_DIR),
.C(IO_ISOL_N),
.X(FPGA_IN)
);
endmodule

16
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf
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@ -60,27 +60,43 @@ bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.
bench1_top = and2_latch
bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench2_top = bin2bcd
bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench3_top = counter
bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench4_top = routing_test
bench4_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
# RS decoder needs 1.5k LUT4, exceeding device capacity
bench5_top = rs_decoder_top
bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench6_top = top_module
bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench7_top = and2_or2
bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench8_top = cavlc_top
bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
#bench9_top = cf_fft_256_8
bench10_top = counter120bitx5
bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench11_top = top
bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench12_top = dct_mac
bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
#bench13_top = des_perf
bench14_top = diffeq_f_systemC
bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
#bench15_top = i2c_master_top
#bench16_top = iir
bench17_top = jpeg_qnr
bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench18_top = multi_enc_decx2x4
bench18_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
#bench19_top = sdc_controller
bench20_top = sha256
bench20_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench21_top = unsigned_mult_80
bench21_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench22_top = io_tc1
bench22_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=