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[Script] Remove signal initialization from testbench generator

This commit is contained in:
tangxifan 2020-11-26 18:23:26 -07:00
parent ba17de5509
commit c237500588
1 changed files with 3 additions and 1 deletions
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4
SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
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@ -59,8 +59,10 @@ write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench
--print_top_testbench \ --print_top_testbench \
--print_preconfig_top_testbench \ --print_preconfig_top_testbench \
--print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \ --print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \
--include_signal_init \
--explicit_port_mapping --explicit_port_mapping
# Exclude signal initialization since it does not help simulator converge
# due to the lack of reset pins for flip-flops
#--include_signal_init
# Write the SDC to run timing analysis for a mapped FPGA fabric # Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/sdc_analysis write_analysis_sdc --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/sdc_analysis