From c237500588fd6d8f8d1345855bf536457dbd1235 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 26 Nov 2020 18:23:26 -0700
Subject: [PATCH] [Script] Remove signal initialization from testbench
 generator

---
 ...water_generate_testbench_using_key_example_script.openfpga | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
index b2cf0f9..fbac2ed 100644
--- a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
+++ b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
@@ -59,8 +59,10 @@ write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench
   --print_top_testbench \
   --print_preconfig_top_testbench \
   --print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \
-  --include_signal_init \
   --explicit_port_mapping
+# Exclude signal initialization since it does not help simulator converge 
+# due to the lack of reset pins for flip-flops
+#--include_signal_init 
 
 # Write the SDC to run timing analysis for a mapped FPGA fabric
 write_analysis_sdc --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/sdc_analysis