Removing commented sections/attributes. Also corrected indentation

ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml

@@ -1,14 +1,14 @@
 <!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k4_frac_cc_sky130nm.xml
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-     - Skywater 130nm PDK
-       - circuit models are binded to the opensource skywater
-         foundry middle-speed (ms) standard cell library
-  -->
+This annotation supports the k4_frac_cc_sky130nm.xml
+- General purpose logic block
+- K = 6, N = 10, I = 40
+- Single mode
+- Routing architecture
+- L = 4, fc_in = 0.15, fc_out = 0.1
+- Skywater 130nm PDK
+- circuit models are binded to the opensource skywater
+foundry middle-speed (ms) standard cell library
+-->
 <openfpga_architecture>
   <technology_library>
     <device_library>
@@ -230,7 +230,6 @@
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
-    <!--circuit_model type="mux" name="mux_1level" is_default="true" prefix="mux_1level" dump_structural_verilog="true"-->
     <circuit_model type="mux" name="mux_1level" prefix="mux_1level" dump_structural_verilog="true">
       <design_technology type="cmos" structure="multi_level" num_level="1" add_const_input="true" const_input_val="1" local_encoder="true"/>
       <input_buffer exist="false"/>
@@ -285,7 +284,6 @@
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
     <circuit_model type="ff" name="sky130_fd_sc_hd__sdfrtp_1" prefix="sky130_fd_sc_hd__sdfrtp_1" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
@@ -305,13 +303,10 @@
       <lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
       <lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
       <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
-      <!--port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/-->
       <port type="input" prefix="in" size="4"/>
       <port type="output" prefix="lut2_out" size="2" lut_frac_level="2" lut_output_mask="2,3"/>
-      <!--port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/-->
       <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
       <port type="sram" prefix="sram" size="16"/>
-      <!--port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="CFGSDFFR" default_val="1"/-->
     </circuit_model>
     <!-- new ccFF  -->
     <circuit_model type="ccff" name="CFGSDFFR" prefix="CFGSDFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
@@ -337,17 +332,8 @@
       <port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
       <port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
 
-	  <!-- 20210106 -->
-	  <!--port type="input" prefix="a2f_i" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/-->
-	  <!--port type="output" prefix="f2a_o" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/-->
-	  <!--port type="output" prefix="a2f_o" lib_name="FPGA_IN" size="1"/-->
-	  <!--port type="input" prefix="f2a_i" lib_name="FPGA_OUT" size="1"/-->
-	  
-	  <!--port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="false" default_val="0" /-->
       <port type="input" prefix="CFG_DONE" lib_name="CFG_DONE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
       <port type="sram" prefix="io_dir" lib_name="FPGA_IO_DIR" size="1" mode_select="true" circuit_model_name="CFGSDFFR" default_val="1"/>
-	  <!-- 20210105 -->
-
     </circuit_model>
     <circuit_model type="hard_logic" name="sky130_fd_sc_hd__mux2_1_wrapper" prefix="sky130_fd_sc_hd__mux2_1_wrapper" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/HDL/common/sky130_fd_sc_hd_wrapper.v">
       <design_technology type="cmos"/>
@@ -382,7 +368,6 @@
     <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
   </direct_connection>
   <tile_annotations>
-    <!--global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/-->
     <global_port name="clk" is_clock="true" default_val="0">
       <tile name="clb" port="clk" x="-1" y="-1"/>
       <tile name="io_top" port="clk" x="-1" y="-1"/>
@@ -390,7 +375,6 @@
       <tile name="io_bottom" port="clk" x="-1" y="-1"/>
       <tile name="io_left" port="clk" x="-1" y="-1"/>
     </global_port>
-    <!--global_port name="Reset" tile_port="clb.reset" is_reset="true" default_val="1"/-->
     <global_port name="reset" is_reset="true" default_val="0">
       <tile name="clb" port="reset" x="-1" y="-1"/>
       <tile name="io_top" port="reset" x="-1" y="-1"/>
@@ -427,19 +411,10 @@
     </pb_type>	
     <!-- physical mode will be the default mode if not specified -->
     <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <!--pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/-->
     <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4"/>
     <pb_type name="clb.fle[physical].fabric.frac_logic.carry_follower" circuit_model_name="sky130_fd_sc_hd__mux2_1_wrapper"/>
     <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfrtp_1"/>
     <!-- Binding operating pb_type to physical pb_type -->
-    <!--pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5"-->
-      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
-      <!--port name="in" physical_mode_port="in[0:2]"/-->
-      <!--port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/-->
-    <!--/pb_type-->
-    <!--pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/-->
-    <!-- Binding operating pb_types in mode 'ble4' -->
-    <!--pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0"-->
     <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4">
       <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
       <port name="in" physical_mode_port="in[0:3]"/>
@@ -448,15 +423,11 @@
     <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
       <!-- Binding operating pb_types in mode 'shift_register' -->
     <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-	<!-- kliao 2021-0112-->
     <pb_type name="clb.fle[soft_adder].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4">
       <port name="in" physical_mode_port="in[0:3]"/>
       <port name="out" physical_mode_port="lut4_out"/>
     </pb_type>
     <pb_type name="clb.fle[soft_adder].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-	
-	
-	
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>

ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml

@@ -1,17 +1,17 @@
 <!-- 
-  Low-cost homogeneous FPGA Architecture.
+Low-cost homogeneous FPGA Architecture.
 
-  - Skywater 130 nm technology
-  - General purpose logic block: 
-    K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
-    with optionally registered outputs
-  - Routing architecture:
-      - 10% L = 1, fc_in = 0.15, Fc_out = 0.10
-      - 10% L = 2, fc_in = 0.15, Fc_out = 0.10
-      - 80% L = 4, fc_in = 0.15, Fc_out = 0.10
-      - 100 routing tracks per channel
+- Skywater 130 nm technology
+- General purpose logic block: 
+K = 4, N = 8, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+with optionally registered outputs
+- Routing architecture:
+- 10% L = 1, fc_in = 0.15, Fc_out = 0.10
+- 10% L = 2, fc_in = 0.15, Fc_out = 0.10
+- 80% L = 4, fc_in = 0.15, Fc_out = 0.10
+- 100 routing tracks per channel
 
-  Authors: Xifan Tang
+Authors: Xifan Tang
 -->
 <architecture>
   <!-- 
@@ -77,10 +77,8 @@
         <site pb_type="io"/>
       </equivalent_sites>
       <clock name="clk" num_pins="1"/>
-      <!--input name="a2f_i" num_pins="1"/-->
       <input name="f2a_i" num_pins="1"/>
       <output name="a2f_o" num_pins="1"/>
-      <!--output name="f2a_o" num_pins="1"/-->
       <input name="sc_in" num_pins="1"/>
       <output name="sc_out" num_pins="1"/>
       <input name="reset" num_pins="1" is_non_clock_global="true"/>
@@ -314,10 +312,8 @@
     <!-- Define input pads begin -->
     <pb_type name="io">
       <clock name="clk" num_pins="1"/>
-      <!--input name="a2f_i" num_pins="1"/-->
       <input name="f2a_i" num_pins="1"/>
       <output name="a2f_o" num_pins="1"/>
-      <!--output name="f2a_o" num_pins="1"/-->
       <input name="sc_in" num_pins="1"/>
       <output name="sc_out" num_pins="1"/>
       <input name="reset" num_pins="1" is_non_clock_global="true"/>
@@ -325,10 +321,8 @@
       <mode name="physical" disabled_in_pack="true">
         <pb_type name="iopad" num_pb="1">
           <clock name="clk" num_pins="1"/>
-          <!--input name="a2f_i" num_pins="1"/-->
           <input name="f2a_i" num_pins="1"/>
           <output name="a2f_o" num_pins="1"/>
-          <!--output name="f2a_o" num_pins="1"/-->
           <input name="sc_in" num_pins="1"/>
           <input name="reset" num_pins="1"/>
           <output name="sc_out" num_pins="1"/>
@@ -351,7 +345,6 @@
             <direct name="ff[0:0]-clk" input="iopad.clk" output="ff[0:0].clk"/>
             <direct name="ff[1:1]-clk" input="iopad.clk" output="ff[1:1].clk"/>
             <direct name="ff[0:0]-D" input="iopad.f2a_i" output="ff[0:0].D" />
-            <!--direct name="ff[1:1]-D" input="iopad.a2f_i" output="ff[1:1].D" /-->
             <direct name="ff[1:1]-D" input="pad.inpad" output="ff[1:1].D"/>
             <direct name="ff[0:0]-DI" input="iopad.sc_in" output="ff[0:0].DI"/>
             <direct name="ff[1:1]-DI" input="ff[0:0].Q" output="ff[1:1].DI"/>
@@ -369,10 +362,8 @@
         </pb_type>
         <interconnect>
           <direct name="direct1" input="io.clk" output="iopad.clk"/>
-          <!--direct name="direct2" input="io.a2f_i" output="iopad.a2f_i"/-->
           <direct name="direct3" input="io.f2a_i" output="iopad.f2a_i"/>
           <direct name="direct4" input="iopad.a2f_o" output="io.a2f_o"/>
-          <!--direct name="direct5" input="iopad.f2a_o" output="io.f2a_o"/-->
           <direct name="direct6" input="io.sc_in" output="iopad.sc_in"/>
           <direct name="direct7" input="iopad.sc_out" output="io.sc_out"/>
           <direct name="direct8" input="io.reset" output="iopad.reset"/>
@@ -509,7 +500,6 @@
                 <direct name="direct4" input="frac_lut4.lut2_out[1:1]" output="carry_follower.a"/>
                 <direct name="direct5" input="frac_lut4.lut2_out[0:0]" output="carry_follower.cin"/>
                 <direct name="direct6" input="carry_follower.cout" output="frac_logic.cout"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
                 <direct name="direct7" input="frac_lut4.lut4_out" output="frac_logic.out"/>
                 <mux name="mux2" input="frac_logic.cin frac_logic.in[2:2]" output="frac_lut4.in[2:2]"/>
               </interconnect>
@@ -673,13 +663,10 @@
         <direct name="shift_register_in" input="clb.reg_in" output="fle[0:0].reg_in">
           <!-- Put all inter-block carry chain delay on this one edge -->
           <delay_constant max="0.16e-9" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/>
-          <!--pack_pattern name="chain" in_port="clb.reg_in" out_port="fle[0:0].reg_in"/-->
         </direct>
         <direct name="shift_register_out" input="fle[7:7].reg_out" output="clb.reg_out">
-          <!--pack_pattern name="chain" in_port="fle[7:7].reg_out" out_port="clb.reg_out"/-->
         </direct>
         <direct name="shift_register_link" input="fle[6:0].reg_out" output="fle[7:1].reg_in">
-          <!--pack_pattern name="chain" in_port="fle[6:0].reg_out" out_port="fle[7:1].reg_in"/-->
         </direct>
         <!-- Scan chain links -->
         <direct name="scan_chain_in" input="clb.sc_in" output="fle[0:0].sc_in">