From ba34ebb4e573d76715561f1d7ce532b734155b40 Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Wed, 13 Jan 2021 00:48:03 -0800 Subject: [PATCH] Removing commented sections/attributes. Also corrected indentation --- ...avel_io_skywater130nm_fdhd_cc_openfpga.xml | 153 ++++++--------- ...n_chain_nonLR_caravel_io_skywater130nm.xml | 185 ++++++++---------- 2 files changed, 148 insertions(+), 190 deletions(-) diff --git a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index e107260..1fff339 100644 --- a/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/ARCH/openfpga_arch_template/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -1,14 +1,14 @@ +This annotation supports the k4_frac_cc_sky130nm.xml +- General purpose logic block +- K = 6, N = 10, I = 40 +- Single mode +- Routing architecture +- L = 4, fc_in = 0.15, fc_out = 0.1 +- Skywater 130nm PDK +- circuit models are binded to the opensource skywater +foundry middle-speed (ms) standard cell library +--> @@ -43,7 +43,7 @@ 10e-12 - + @@ -79,7 +79,7 @@ 10e-12 - + @@ -127,7 +127,7 @@ 10e-12 - + @@ -160,12 +160,12 @@ + OpenFPGA requires the following truth table for the MUX2 + When the select signal sel is enabled, the first input, i.e., in0 + will be propagated to the output, i.e., out + If your standard cell provider does not offer the exact truth table, + you can simply swap the inputs as shown in the example below + --> @@ -183,7 +183,7 @@ - + @@ -192,7 +192,7 @@ - + @@ -230,8 +230,7 @@ - - + @@ -240,7 +239,7 @@ - + @@ -249,7 +248,7 @@ - + @@ -267,7 +266,7 @@ - + @@ -285,7 +284,6 @@ - @@ -305,28 +303,25 @@ - - + - - - - - - - - - - - - - - - + + + + + + + + + + + + + @@ -336,18 +331,9 @@ - - - - - - - - - - - + + @@ -382,27 +368,25 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + - + @@ -414,9 +398,9 @@ - + - + @@ -427,36 +411,23 @@ - - + - - - - - - - - - + - + - - + - - - diff --git a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index d110543..f141b76 100644 --- a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -1,27 +1,27 @@ @@ -68,19 +68,17 @@ + If you need to register the I/O, define clocks in the circuit models + These clocks can be handled in back-end + --> - - @@ -202,7 +200,7 @@ - + @@ -212,7 +210,7 @@ - + @@ -222,7 +220,7 @@ - + @@ -232,30 +230,30 @@ - + + models. We are modifying the delay values however, to include metal C and R, which allows more architecture + experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS + (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of + 45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping + RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately + lined up with Stratix IV. + We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm). + Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm). + The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file + by 2.5x when looking up in Jeff's tables. + The delay values are lined up with Stratix IV, which has an architecture similar to this + proposed FPGA, and which is also 40 nm + C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage + 4x minimum drive strength buffer. --> - + @@ -266,28 +264,28 @@ + book area formula. This means the mux transistors are about 5x minimum drive strength. + We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large + mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume + the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed + by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified + buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive. + I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout + (diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples. + The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by + 2.5x when looking up in Jeff's tables. + Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. + This also leads to the switch being 46% of the total wire delay, which is reasonable. --> - + + With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems + reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. --> @@ -314,21 +312,17 @@ - - - + - - @@ -351,7 +345,6 @@ - @@ -369,10 +362,8 @@ - - @@ -441,10 +432,10 @@ + the 4 inputs of fracturable LUT4 are no longer equivalent, + because the 4th input can not be switched when the dual-LUT3 modes are used. + So pin equivalence should be applied to the first 3 inputs only + --> @@ -457,9 +448,9 @@ - @@ -472,7 +463,7 @@ - + @@ -490,7 +481,7 @@ - + @@ -509,7 +500,6 @@ - @@ -528,8 +518,8 @@ - - + + @@ -566,20 +556,20 @@ - + - - + + --> 261e-12 261e-12 @@ -648,13 +638,13 @@ + The global local routing is going to compensate the loss in routability + --> - + in[2]. Such twisted connection is not expected. + I[0] should be connected to in[0] + --> + @@ -662,24 +652,21 @@ + By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, + then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more + naive specification). + --> - - - + + + - - -