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[Script] Force a fixed number of clock cycles in simulation to avoid false-positive

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tangxifan 2020-12-02 17:50:23 -07:00
parent a19c9bdbda
commit b966829566
1 changed files with 1 additions and 1 deletions
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SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
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@ -11,7 +11,7 @@
As the FPGA core does not share the clock with Caravel SoC As the FPGA core does not share the clock with Caravel SoC
the actual clock frequency could be higher the actual clock frequency could be higher
--> -->
<operating frequency="50e6" num_cycles="auto" slack="0.2"/> <operating frequency="50e6" num_cycles="100" slack="0.2"/>
<!-- Use 50MHz as the Caravel SoC can operate at 50MHz <!-- Use 50MHz as the Caravel SoC can operate at 50MHz
As the FPGA core does not share the clock with Caravel SoC As the FPGA core does not share the clock with Caravel SoC
the actual programming clock frequency could be higher the actual programming clock frequency could be higher