From b966829566a5765ed09bbb2c6947aa95b3eabdab Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 2 Dec 2020 17:50:23 -0700
Subject: [PATCH] [Script] Force a fixed number of clock cycles in simulation
 to avoid false-positive

---
 SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml b/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
index 92cf793..d9f8401 100644
--- a/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
+++ b/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
@@ -11,7 +11,7 @@
          As the FPGA core does not share the clock with Caravel SoC
          the actual clock frequency could be higher 
       -->
-    <operating frequency="50e6" num_cycles="auto" slack="0.2"/>
+    <operating frequency="50e6" num_cycles="100" slack="0.2"/>
     <!-- Use 50MHz as the Caravel SoC can operate at 50MHz 
          As the FPGA core does not share the clock with Caravel SoC
          the actual programming clock frequency could be higher