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[MISC] Bug fixes for wrong paths in task configuration files; typo in arch files

This commit is contained in:
tangxifan 2021-04-01 21:16:08 -06:00
parent 4aea849cf9
commit b22584e7a1
13 changed files with 13 additions and 10 deletions
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2
ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -503,7 +503,7 @@
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out"> <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
<!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux --> <!-- Combine the delay of LUT4/LUT3 output MUX and fabric output mux -->
<delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/> <delay_constant max="${LUT4_OUT_TO_FLE_OUT_DELAY}" in_port="lut4.out" out_port="ble4.out"/>
<delay_constant max="${FF1_Q_TO_FILE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/> <delay_constant max="${FF1_Q_TO_FLE_OUT_DELAY}" in_port="ff.Q" out_port="ble4.out"/>
</mux> </mux>
</interconnect> </interconnect>
</pb_type> </pb_type>

2
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
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@ -14,7 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

2
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
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@ -14,7 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

2
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
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@ -14,7 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_fabric/config/task_template.conf
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@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_sdc/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_2x2/generate_testbench/config/task_template.conf
View File

@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

2
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_fabric/config/task_template.conf
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@ -14,7 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

2
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_sdc/config/task_template.conf
View File

@ -14,7 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

2
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_customhd_12x12/generate_testbench/config/task_template.conf
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@ -14,7 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_chd_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

2
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
View File

@ -14,7 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

2
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
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@ -14,7 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

2
SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
View File

@ -14,7 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml arch_variable_file=${SKYWATER_OPENFPGA_HOME}/ARCH/timing_annotation/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga