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[Script] Patch example openfpga shell script to manage clock routing in VPR

This commit is contained in:
tangxifan 2020-11-17 14:27:14 -07:00
parent 0e2ee8a0cc
commit a97598cef9
3 changed files with 3 additions and 3 deletions
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2
SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
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@ -6,7 +6,7 @@
# - fabric hierarchy description for ICC2's hierarchical flow # - fabric hierarchy description for ICC2's hierarchical flow
# - Timing/Design constraints # - Timing/Design constraints
# #
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
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@ -6,7 +6,7 @@
# - fabric hierarchy description for ICC2's hierarchical flow # - fabric hierarchy description for ICC2's hierarchical flow
# - Timing/Design constraints # - Timing/Design constraints
# #
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
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@ -6,7 +6,7 @@
# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime # - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
# #
#--write_rr_graph example_rr_graph.xml #--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}