From a97598cef9a635e3f4ba7fca8e8878a2657711a1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 17 Nov 2020 14:27:14 -0700 Subject: [PATCH] [Script] Patch example openfpga shell script to manage clock routing in VPR --- .../skywater_generate_fabric_using_key_example_script.openfpga | 2 +- .../skywater_generate_sdc_using_key_example_script.openfpga | 2 +- ...kywater_generate_testbench_using_key_example_script.openfpga | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga index 971796f..1d9e37e 100644 --- a/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga +++ b/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga @@ -6,7 +6,7 @@ # - fabric hierarchy description for ICC2's hierarchical flow # - Timing/Design constraints # -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga index 2371794..b9b0b35 100644 --- a/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga +++ b/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga @@ -6,7 +6,7 @@ # - fabric hierarchy description for ICC2's hierarchical flow # - Timing/Design constraints # -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga index ecd657d..38e4631 100644 --- a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga +++ b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga @@ -6,7 +6,7 @@ # - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime # #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}