riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

correct PDK path

This commit is contained in:
Tarachand Pagarani 2020-12-08 07:21:41 -08:00
parent 053afc7c45
commit 9fc40cd919
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ARCH/openfpga_arch_template/ql_ap3_8x8_arch_vpr_routing_skywater130nm_fdhd_cc_openfpga.xml
View File

@ -86,7 +86,7 @@
If your standard cell provider does not offer the exact truth table, If your standard cell provider does not offer the exact truth table,
you can simply swap the inputs as shown in the example below you can simply swap the inputs as shown in the example below
--> -->
<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"> <circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${SKYWATER_OPENFPGA_HOME}/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
<design_technology type="cmos" topology="OR"/> <design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>