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[Doc] Add SOFA CHD to documentation. Clean up redundant document between HD FPGA IPs

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tangxifan 2020-12-09 16:18:04 -07:00
parent d9e965cf3b
commit 9f82ac7636
15 changed files with 84 additions and 1746 deletions
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DOC/source/datasheet/index.rst
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sofa_hd/index sofa_hd/index
qlsofa_hd/index qlsofa_hd/index
sofa_chd/index

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.. _datasheet_sofa_hd: .. _datasheet_qlsofa_hd:
QLSOFA HD QLSOFA HD
QLSOFA HD QLSOFA HD

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@ -8,29 +8,5 @@ Circuit Designs
I/O Circuit I/O Circuit
^^^^^^^^^^^ ^^^^^^^^^^^
As shown in :numref:`fig_qlsofa_hd_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_qlsofa_hd_fpga_arch`) is an digital I/O cell with SOFA CHD FPGA share the same I/O circuit design as SOFA HD FPGA.
See details at :ref:`sofa_hd_circuit_design_io`.
- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized.
.. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality!
- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid
- ``SOC_OUT`` port outputs any random signal when the I/O is in input mode
- ``FPGA_IN`` port is driven by any random signal when the I/O is output mode
- An internal configurable memory element to control the direction of I/O cell
The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where
- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode
- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode
.. _fig_qlsofa_hd_embedded_io_schematic:
.. figure:: ./figures/qlsofa_hd_embedded_io_schematic.svg
:scale: 30%
:alt: Schematic of embedded I/O cell used in FPGA
Schematic of embedded I/O cell used in FPGA

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@ -8,21 +8,8 @@ Architecture
Floorplan Floorplan
^^^^^^^^^ ^^^^^^^^^
QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA.
:numref:`fig_qlsofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric. See details at :ref:`sofa_hd_fpga_arch_floorplan`.
The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric.
I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`qlsofa_hd_io_resource`).
.. _fig_qlsofa_hd_fpga_arch:
.. figure:: ./figures/qlsofa_hd_fpga_arch.svg
:scale: 25%
:alt: Tile-based FPGA architecture
Tile-based FPGA architecture
.. _qlsofa_hd_fpga_arch_tiles:
Tiles Tiles
^^^^^ ^^^^^
@ -64,19 +51,5 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra
Scan-chain Scan-chain
^^^^^^^^^^ ^^^^^^^^^^
There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`qlsofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_qlsofa_hd_fabric_scan_chain`. QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA.
See details at :ref:`sofa_hd_fpga_arch_scan_chain`.
When `Test_en` signal is active, users can
- overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port
- readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port.
.. _fig_qlsofa_hd_fabric_scan_chain:
.. figure:: ./figures/qlsofa_hd_fabric_scan_chain.svg
:scale: 25%
:alt: Built-in scan-chain across FPGA
Built-in scan-chain across FPGA

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Pin Assignment Pin Assignment
^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^
The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`. The QLSOFA HD FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`.
Among the 144 I/Os, Among the 144 I/Os,
@ -26,14 +26,14 @@ Among the 144 I/Os,
:scale: 20% :scale: 20%
:alt: I/O arrangement of FPGA IP :alt: I/O arrangement of FPGA IP
I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface I/O arrangement of QLSOFA HD FPGA IP: switchable between logic analyzer and wishbone bus interface
.. _io_resource_qlsofa_hd_external_io: .. _io_resource_qlsofa_hd_external_io:
External I/Os External I/Os
^^^^^^^^^^^^^ ^^^^^^^^^^^^^
A SOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os. A QLSOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os.
Full details are summarized in the following table. Full details are summarized in the following table.

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.. _datasheet_sofa_chd:
SOFA CHD
SOFA CHD
--------
.. toctree::
:maxdepth: 2
sofa_chd_fpga_arch
sofa_chd_io_resource
sofa_chd_clb_arch
sofa_chd_circuit_design

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.. _sofa_chd_circuit_design:
Circuit Designs
---------------
.. _sofa_chd_circuit_design_io:
I/O Circuit
^^^^^^^^^^^
SOFA CHD FPGA share the same I/O circuit design as SOFA HD FPGA.
See details at :ref:`sofa_hd_circuit_design_io`.

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.. _sofa_chd_clb_arch:
Configurable Logic Block
------------------------
The SOFA CHD FPGA IP share the same *Configurable Logic Block* (CLB) architecture as QLSOFA HD FPGA IP.
See details at :ref:`qlsofa_hd_clb_arch`.

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.. _sofa_chd_fpga_arch:
Architecture
-------------
SOFA CHD FPGA share the same architecture as QLSOFA HD FPGA.
See full details at :ref:`qlsofa_hd_fpga_arch`.

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.. _sofa_chd_io_resource:
I/O Resources
-------------
The SOFA CHD FPGA IP share the same I/O resource arragement as QLSOFA HD FPGA IP.
See details at :ref:`qlsofa_hd_io_resource`.

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@ -7,27 +7,27 @@ The High Density (HD) FPGAs are embedded FPGAs built with the Skywater 130nm Hig
.. table:: Logic capacity of High Density (HD) FPGA IPs .. table:: Logic capacity of High Density (HD) FPGA IPs
+-------------------------------+------------+-----------+ +-------------------------------+------------+-----------+----------+
| Resource/Capacity | SOFA HD | QLSOFA HD | | Resource/Capacity | SOFA HD | QLSOFA HD | SOFA CHD |
+===============================+============+===========+ +===============================+============+===========+==========+
| Look-Up Tables [1]_ | 1152 | 1152 | | Look-Up Tables [1]_ | 1152 | 1152 | 1152 |
+-------------------------------+------------+-----------+ +-------------------------------+------------+-----------+----------+
| Flip-flops | 2304 | 2304 | | Flip-flops | 2304 | 2304 | 2304 |
+-------------------------------+------------+-----------+ +-------------------------------+------------+-----------+----------+
| Soft Adders [2]_ | N/A | 1152 | | Soft Adders [2]_ | N/A | 1152 | 1152 |
+-------------------------------+------------+-----------+ +-------------------------------+------------+-----------+----------+
| Routing Channel Width [3]_ | 40 | 60 | | Routing Channel Width [3]_ | 40 | 60 | 60 |
+-------------------------------+------------+-----------+ +-------------------------------+------------+-----------+----------+
| Max. Configuration Speed [4]_ | 50MHz | 50MHz | | Max. Configuration Speed [4]_ | 50MHz | 50MHz | 50MHz |
+-------------------------------+------------+-----------+ +-------------------------------+------------+-----------+----------+
| Max. Operating Speed [4]_ | 50MHz | 50 MHz | | Max. Operating Speed [4]_ | 50MHz | 50 MHz | 50MHz |
+-------------------------------+------------+-----------+ +-------------------------------+------------+-----------+----------+
| User I/O Pins [5]_ | 144 | 144 | | User I/O Pins [5]_ | 144 | 144 | 144 |
+-------------------------------+------------+-----------+ +-------------------------------+------------+-----------+----------+
| Max. I/O Speed [4]_ | 33MHz | 33 MHz | | Max. I/O Speed [4]_ | 33MHz | 33MHz | 33MHz |
+-------------------------------+------------+-----------+ +-------------------------------+------------+-----------+----------+
| Core Voltage | 1.8V | 1.8V | | Core Voltage | 1.8V | 1.8V | 1.8V |
+-------------------------------+------------+-----------+ +-------------------------------+------------+-----------+----------+
.. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT. .. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT.

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You can adapt this file completely to your liking, but it should at least You can adapt this file completely to your liking, but it should at least
contain the root `toctree` directive. contain the root `toctree` directive.
Welcome to SKywater-OpenFPGA documentation! Welcome to SOFA documentation!
=========================================== ==============================
.. toctree:: .. toctree::
:caption: Device Family :caption: Device Family