From 9f82ac7636cbbf2651c512955f991f6c24ecba8d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 9 Dec 2020 16:18:04 -0700 Subject: [PATCH] [Doc] Add SOFA CHD to documentation. Clean up redundant document between HD FPGA IPs --- DOC/source/datasheet/index.rst | 2 + .../qlsofa_hd_embedded_io_schematic.svg | 253 ---- .../figures/qlsofa_hd_fabric_scan_chain.svg | 320 ----- .../qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg | 1089 ----------------- DOC/source/datasheet/qlsofa_hd/index.rst | 2 +- .../qlsofa_hd/qlsofa_hd_circuit_design.rst | 28 +- .../qlsofa_hd/qlsofa_hd_fpga_arch.rst | 35 +- .../qlsofa_hd/qlsofa_hd_io_resource.rst | 6 +- DOC/source/datasheet/sofa_chd/index.rst | 16 + .../sofa_chd/sofa_chd_circuit_design.rst | 12 + .../datasheet/sofa_chd/sofa_chd_clb_arch.rst | 7 + .../datasheet/sofa_chd/sofa_chd_fpga_arch.rst | 7 + .../sofa_chd/sofa_chd_io_resource.rst | 7 + DOC/source/device/hd_fpga/hd_device_comp.rst | 42 +- DOC/source/index.rst | 4 +- 15 files changed, 84 insertions(+), 1746 deletions(-) delete mode 100644 DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_embedded_io_schematic.svg delete mode 100644 DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fabric_scan_chain.svg delete mode 100644 DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg create mode 100644 DOC/source/datasheet/sofa_chd/index.rst create mode 100644 DOC/source/datasheet/sofa_chd/sofa_chd_circuit_design.rst create mode 100644 DOC/source/datasheet/sofa_chd/sofa_chd_clb_arch.rst create mode 100644 DOC/source/datasheet/sofa_chd/sofa_chd_fpga_arch.rst create mode 100644 DOC/source/datasheet/sofa_chd/sofa_chd_io_resource.rst diff --git a/DOC/source/datasheet/index.rst b/DOC/source/datasheet/index.rst index ef6404f..1aaddde 100644 --- a/DOC/source/datasheet/index.rst +++ b/DOC/source/datasheet/index.rst @@ -7,3 +7,5 @@ sofa_hd/index qlsofa_hd/index + + sofa_chd/index diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_embedded_io_schematic.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_embedded_io_schematic.svg deleted file mode 100644 index 75482cb..0000000 --- a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_embedded_io_schematic.svg +++ /dev/null @@ -1,253 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Produced by OmniGraffle 7.18\n2020-11-19 23:01:04 +0000 - - switch - - boundary - - - - - - - - - - - - - CCFF_IN - - - - - - - - CCFF_OUT - - - - - - - - FPGA Fabric - - - - - SoC Interface - - - - - - - - base - - - SOC_IN - - - - - SOC_OUT - - - - - - - - - - - - - - - - - FPGA_OUT - - - - - FPGA_IN - - - - - - - - - - - - SOC_DIR - - - - - - - - - - - - - - - - - - - - - - - - - - FF - - - - - - - - - - - - PROG_CLK - - - - - - - - - - - IO_ISOL_N - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - output pin - - - - - input pin - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fabric_scan_chain.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fabric_scan_chain.svg deleted file mode 100644 index 0bf9cc5..0000000 --- a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fabric_scan_chain.svg +++ /dev/null @@ -1,320 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Produced by OmniGraffle 7.18\n2020-11-17 17:11:00 +0000 - - fpga_arch - - legend - - - - - - - FPGA - - - - - - - - x - - - - - - - - y - - - - - chain - - - - - CLB - [1][12] - - - - - - - - SC_HEAD - - - - - - - CLB - [1][11] - - - - - - - - - - - … - - - - - - - CLB - [1][2] - - - - - - - - - - CLB - [1][1] - - - - - - - - - - CLB - [2][12] - - - - - - - - - - CLB - [2][11] - - - - - - - - - - - … - - - - - - - CLB - [2][2] - - - - - - - - - - CLB - [2][1] - - - - - - - - - - - - - CLB - [11][12] - - - - - - - - - - CLB - [11][11] - - - - - - - - - - - … - - - - - - - CLB - [11][2] - - - - - - - - - - CLB - [11][1] - - - - - - - - - - CLB - [12][12] - - - - - - - - - - CLB - [12][11] - - - - - - - - - - - … - - - - - - - CLB - [12][2] - - - - - - - - - - CLB - [12][1] - - - - - - - - - - - … - - - - - SC_TAIL - - - - - … - - - - - … - - - - - … - - - - - … - - - - - diff --git a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg b/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg deleted file mode 100644 index 59678b3..0000000 --- a/DOC/source/datasheet/qlsofa_hd/figures/qlsofa_hd_fpga_arch.svg +++ /dev/null @@ -1,1089 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Produced by OmniGraffle 7.18\n2020-11-17 16:24:14 +0000 - - fpga_arch - - tiles - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - legend - - - Programmable Fabric - - - - - - - - - - - Routing Tracks - - - - - - - - - - Tile - - - - - - - I/O TileA - - - - - - - - - - - - - - I/O TileB - - - - - - - - - - - 12 - - - - - - - - - 12 - - - - - - - - tile_details - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Tile - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Switch - Block - - - - - - - Configurable - Logic - Block - - - - - - - - - - - ... - - - - - ... - - - - - ... - - - - - ... - - - - - ... - - - - - ... - - - - - - - X-direction - Connection - Block - - - - - - - Y-direction - Connection - Block - - - - - - - - - - - diff --git a/DOC/source/datasheet/qlsofa_hd/index.rst b/DOC/source/datasheet/qlsofa_hd/index.rst index 09e8665..b736ea8 100644 --- a/DOC/source/datasheet/qlsofa_hd/index.rst +++ b/DOC/source/datasheet/qlsofa_hd/index.rst @@ -1,4 +1,4 @@ -.. _datasheet_sofa_hd: +.. _datasheet_qlsofa_hd: QLSOFA HD QLSOFA HD diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst index 90d527b..0960a72 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_circuit_design.rst @@ -8,29 +8,5 @@ Circuit Designs I/O Circuit ^^^^^^^^^^^ -As shown in :numref:`fig_qlsofa_hd_embedded_io_schematic`, the I/O circuit used in the I/O tiles of the FPGA fabric (see :numref:`fig_qlsofa_hd_fpga_arch`) is an digital I/O cell with - -- An **active-low** I/O isolation signal ``IO_ISOL_N`` to set the I/O in input mode. This is to avoid any unexpected output signals to damage circuits outside the FPGA due to configurable memories are not properly initialized. - - .. warning:: This feature may not be needed if the configurable memory cell has a built-in set/reset functionality! - -- An internal protection circuitry to ensure clean signals at all the SOC I/O ports. This is to avoid - - - ``SOC_OUT`` port outputs any random signal when the I/O is in input mode - - ``FPGA_IN`` port is driven by any random signal when the I/O is output mode - -- An internal configurable memory element to control the direction of I/O cell - -The truth table of the I/O cell is consistent with the GPIO cell of Caravel SoC, where - -- When configuration bit (FF output) is logic ``1``, the I/O cell is in input mode - -- When configuration bit (FF output) is logic ``0``, the I/O cell is in output mode - -.. _fig_qlsofa_hd_embedded_io_schematic: - -.. figure:: ./figures/qlsofa_hd_embedded_io_schematic.svg - :scale: 30% - :alt: Schematic of embedded I/O cell used in FPGA - - Schematic of embedded I/O cell used in FPGA +SOFA CHD FPGA share the same I/O circuit design as SOFA HD FPGA. +See details at :ref:`sofa_hd_circuit_design_io`. diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst index f1d079d..ae457b0 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_fpga_arch.rst @@ -8,21 +8,8 @@ Architecture Floorplan ^^^^^^^^^ - -:numref:`fig_qlsofa_hd_fpga_arch` shows an overview on the architecture of the embedded FPGA fabric. -The FPGA follows a homogeneous architecture which only contains single type of tiles in the center fabric. -I/O tiles are placed at the boundary of the FPGA to interface with GPIOs and RISC-V processors (see details in :ref:`qlsofa_hd_io_resource`). - -.. _fig_qlsofa_hd_fpga_arch: - -.. figure:: ./figures/qlsofa_hd_fpga_arch.svg - :scale: 25% - :alt: Tile-based FPGA architecture - - Tile-based FPGA architecture - - -.. _qlsofa_hd_fpga_arch_tiles: +QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA. +See details at :ref:`sofa_hd_fpga_arch_floorplan`. Tiles ^^^^^ @@ -64,19 +51,5 @@ The FPGA architecture follows a tile-based organization, to exploit the fine-gra Scan-chain ^^^^^^^^^^ -There is a built-in scan-chain in the FPGA which connects the the `sc_in` and `sc_out` ports of CLBs in a chain (see details in :ref:`qlsofa_hd_clb_arch_scan_chain`), as illustrated in :numref:`fig_qlsofa_hd_fabric_scan_chain`. - -When `Test_en` signal is active, users can - -- overwrite the contents of all the D-type flip-flops in the FPGA by feeding signals to the `SC_HEAD` port -- readback the contents of all the D-type flip-flops in the FPGA through the `SC_TAIL` port. - -.. _fig_qlsofa_hd_fabric_scan_chain: - -.. figure:: ./figures/qlsofa_hd_fabric_scan_chain.svg - :scale: 25% - :alt: Built-in scan-chain across FPGA - - Built-in scan-chain across FPGA - - +QLSOFA HD FPGA share the same floroplan as SOFA HD FPGA. +See details at :ref:`sofa_hd_fpga_arch_scan_chain`. diff --git a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst index fc2badb..f8cbf4f 100644 --- a/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst +++ b/DOC/source/datasheet/qlsofa_hd/qlsofa_hd_io_resource.rst @@ -6,7 +6,7 @@ I/O Resources Pin Assignment ^^^^^^^^^^^^^^ -The *High-Density* (HD) FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`. +The QLSOFA HD FPGA IP has 144 data I/O pins as shown in :numref:`fig_qlsofa_hd_fpga_io_switch`. Among the 144 I/Os, @@ -26,14 +26,14 @@ Among the 144 I/Os, :scale: 20% :alt: I/O arrangement of FPGA IP - I/O arrangement of *High-Density* (HD) FPGA IP: switchable between logic analyzer and wishbone bus interface + I/O arrangement of QLSOFA HD FPGA IP: switchable between logic analyzer and wishbone bus interface .. _io_resource_qlsofa_hd_external_io: External I/Os ^^^^^^^^^^^^^ -A SOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os. +A QLSOFA HD FPGA IP contains 37 external I/O pins, including 27 data I/Os and 10 control I/Os. Full details are summarized in the following table. diff --git a/DOC/source/datasheet/sofa_chd/index.rst b/DOC/source/datasheet/sofa_chd/index.rst new file mode 100644 index 0000000..a35e5fe --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/index.rst @@ -0,0 +1,16 @@ +.. _datasheet_sofa_chd: + SOFA CHD + +SOFA CHD +-------- + +.. toctree:: + :maxdepth: 2 + + sofa_chd_fpga_arch + + sofa_chd_io_resource + + sofa_chd_clb_arch + + sofa_chd_circuit_design diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_circuit_design.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_circuit_design.rst new file mode 100644 index 0000000..911f429 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_circuit_design.rst @@ -0,0 +1,12 @@ +.. _sofa_chd_circuit_design: + +Circuit Designs +--------------- + +.. _sofa_chd_circuit_design_io: + +I/O Circuit +^^^^^^^^^^^ + +SOFA CHD FPGA share the same I/O circuit design as SOFA HD FPGA. +See details at :ref:`sofa_hd_circuit_design_io`. diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_clb_arch.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_clb_arch.rst new file mode 100644 index 0000000..933fcb5 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_clb_arch.rst @@ -0,0 +1,7 @@ +.. _sofa_chd_clb_arch: + +Configurable Logic Block +------------------------ + +The SOFA CHD FPGA IP share the same *Configurable Logic Block* (CLB) architecture as QLSOFA HD FPGA IP. +See details at :ref:`qlsofa_hd_clb_arch`. diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_fpga_arch.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_fpga_arch.rst new file mode 100644 index 0000000..2380b03 --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_fpga_arch.rst @@ -0,0 +1,7 @@ +.. _sofa_chd_fpga_arch: + +Architecture +------------- + +SOFA CHD FPGA share the same architecture as QLSOFA HD FPGA. +See full details at :ref:`qlsofa_hd_fpga_arch`. diff --git a/DOC/source/datasheet/sofa_chd/sofa_chd_io_resource.rst b/DOC/source/datasheet/sofa_chd/sofa_chd_io_resource.rst new file mode 100644 index 0000000..5b4b96f --- /dev/null +++ b/DOC/source/datasheet/sofa_chd/sofa_chd_io_resource.rst @@ -0,0 +1,7 @@ +.. _sofa_chd_io_resource: + +I/O Resources +------------- + +The SOFA CHD FPGA IP share the same I/O resource arragement as QLSOFA HD FPGA IP. +See details at :ref:`qlsofa_hd_io_resource`. diff --git a/DOC/source/device/hd_fpga/hd_device_comp.rst b/DOC/source/device/hd_fpga/hd_device_comp.rst index 940efe4..6d0bb33 100644 --- a/DOC/source/device/hd_fpga/hd_device_comp.rst +++ b/DOC/source/device/hd_fpga/hd_device_comp.rst @@ -7,27 +7,27 @@ The High Density (HD) FPGAs are embedded FPGAs built with the Skywater 130nm Hig .. table:: Logic capacity of High Density (HD) FPGA IPs - +-------------------------------+------------+-----------+ - | Resource/Capacity | SOFA HD | QLSOFA HD | - +===============================+============+===========+ - | Look-Up Tables [1]_ | 1152 | 1152 | - +-------------------------------+------------+-----------+ - | Flip-flops | 2304 | 2304 | - +-------------------------------+------------+-----------+ - | Soft Adders [2]_ | N/A | 1152 | - +-------------------------------+------------+-----------+ - | Routing Channel Width [3]_ | 40 | 60 | - +-------------------------------+------------+-----------+ - | Max. Configuration Speed [4]_ | 50MHz | 50MHz | - +-------------------------------+------------+-----------+ - | Max. Operating Speed [4]_ | 50MHz | 50 MHz | - +-------------------------------+------------+-----------+ - | User I/O Pins [5]_ | 144 | 144 | - +-------------------------------+------------+-----------+ - | Max. I/O Speed [4]_ | 33MHz | 33 MHz | - +-------------------------------+------------+-----------+ - | Core Voltage | 1.8V | 1.8V | - +-------------------------------+------------+-----------+ + +-------------------------------+------------+-----------+----------+ + | Resource/Capacity | SOFA HD | QLSOFA HD | SOFA CHD | + +===============================+============+===========+==========+ + | Look-Up Tables [1]_ | 1152 | 1152 | 1152 | + +-------------------------------+------------+-----------+----------+ + | Flip-flops | 2304 | 2304 | 2304 | + +-------------------------------+------------+-----------+----------+ + | Soft Adders [2]_ | N/A | 1152 | 1152 | + +-------------------------------+------------+-----------+----------+ + | Routing Channel Width [3]_ | 40 | 60 | 60 | + +-------------------------------+------------+-----------+----------+ + | Max. Configuration Speed [4]_ | 50MHz | 50MHz | 50MHz | + +-------------------------------+------------+-----------+----------+ + | Max. Operating Speed [4]_ | 50MHz | 50 MHz | 50MHz | + +-------------------------------+------------+-----------+----------+ + | User I/O Pins [5]_ | 144 | 144 | 144 | + +-------------------------------+------------+-----------+----------+ + | Max. I/O Speed [4]_ | 33MHz | 33MHz | 33MHz | + +-------------------------------+------------+-----------+----------+ + | Core Voltage | 1.8V | 1.8V | 1.8V | + +-------------------------------+------------+-----------+----------+ .. [1] counted by 4-input fracturable Look-Up Tables (LUTs), each of which can operate as dual-output 3-input LUTs or single-output 4-input LUT. diff --git a/DOC/source/index.rst b/DOC/source/index.rst index cbf7d6e..9600c26 100644 --- a/DOC/source/index.rst +++ b/DOC/source/index.rst @@ -3,8 +3,8 @@ You can adapt this file completely to your liking, but it should at least contain the root `toctree` directive. -Welcome to SKywater-OpenFPGA documentation! -=========================================== +Welcome to SOFA documentation! +============================== .. toctree:: :caption: Device Family