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[FPGA1212_v1.1] Added PostPnR files

This commit is contained in:
Ganesh Gore 2020-12-02 01:43:58 -07:00
parent f385c0ca11
commit 923a502c24
7 changed files with 306106 additions and 0 deletions
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100362
FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.fm.v Normal file
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FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.gds.gz Normal file
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FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.lef Normal file
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@ -0,0 +1,352 @@
VERSION 5.7 ;
BUSBITCHARS "[]" ;
UNITS
DATABASE MICRONS 1000 ;
END UNITS
MANUFACTURINGGRID 0.005 ;
LAYER li1
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.46 ;
WIDTH 0.17 ;
END li1
LAYER mcon
TYPE CUT ;
END mcon
LAYER met1
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.34 ;
WIDTH 0.14 ;
END met1
LAYER via
TYPE CUT ;
END via
LAYER met2
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.46 ;
WIDTH 0.14 ;
END met2
LAYER via2
TYPE CUT ;
END via2
LAYER met3
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.68 ;
WIDTH 0.3 ;
END met3
LAYER via3
TYPE CUT ;
END via3
LAYER met4
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.92 ;
WIDTH 0.3 ;
END met4
LAYER via4
TYPE CUT ;
END via4
LAYER met5
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 3.4 ;
WIDTH 1.6 ;
END met5
LAYER nwell
TYPE MASTERSLICE ;
END nwell
LAYER pwell
TYPE MASTERSLICE ;
END pwell
VIA L1M1_PR
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.145 -0.115 0.145 0.115 ;
END L1M1_PR
VIA L1M1_PR_R
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.115 -0.145 0.115 0.145 ;
END L1M1_PR_R
VIA L1M1_PR_M
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.115 -0.145 0.115 0.145 ;
END L1M1_PR_M
VIA L1M1_PR_MR
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.145 -0.115 0.145 0.115 ;
END L1M1_PR_MR
VIA L1M1_PR_C
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.145 -0.145 0.145 0.145 ;
END L1M1_PR_C
VIA M1M2_PR
LAYER met1 ;
RECT -0.16 -0.13 0.16 0.13 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met2 ;
RECT -0.13 -0.16 0.13 0.16 ;
END M1M2_PR
VIA M1M2_PR_Enc
LAYER met1 ;
RECT -0.16 -0.13 0.16 0.13 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met2 ;
RECT -0.16 -0.13 0.16 0.13 ;
END M1M2_PR_Enc
VIA M1M2_PR_R
LAYER met1 ;
RECT -0.13 -0.16 0.13 0.16 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met2 ;
RECT -0.16 -0.13 0.16 0.13 ;
END M1M2_PR_R
VIA M1M2_PR_R_Enc
LAYER met1 ;
RECT -0.13 -0.16 0.13 0.16 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met2 ;
RECT -0.13 -0.16 0.13 0.16 ;
END M1M2_PR_R_Enc
VIA M1M2_PR_M
LAYER met1 ;
RECT -0.16 -0.13 0.16 0.13 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met2 ;
RECT -0.16 -0.13 0.16 0.13 ;
END M1M2_PR_M
VIA M1M2_PR_M_Enc
LAYER met1 ;
RECT -0.16 -0.13 0.16 0.13 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met2 ;
RECT -0.13 -0.16 0.13 0.16 ;
END M1M2_PR_M_Enc
VIA M1M2_PR_MR
LAYER met1 ;
RECT -0.13 -0.16 0.13 0.16 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met2 ;
RECT -0.13 -0.16 0.13 0.16 ;
END M1M2_PR_MR
VIA M1M2_PR_MR_Enc
LAYER met1 ;
RECT -0.13 -0.16 0.13 0.16 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met2 ;
RECT -0.16 -0.13 0.16 0.13 ;
END M1M2_PR_MR_Enc
VIA M1M2_PR_C
LAYER met1 ;
RECT -0.16 -0.16 0.16 0.16 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met2 ;
RECT -0.16 -0.16 0.16 0.16 ;
END M1M2_PR_C
VIA M2M3_PR
LAYER met2 ;
RECT -0.14 -0.185 0.14 0.185 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR
VIA M2M3_PR_R
LAYER met2 ;
RECT -0.185 -0.14 0.185 0.14 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR_R
VIA M2M3_PR_M
LAYER met2 ;
RECT -0.14 -0.185 0.14 0.185 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR_M
VIA M2M3_PR_MR
LAYER met2 ;
RECT -0.185 -0.14 0.185 0.14 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR_MR
VIA M2M3_PR_C
LAYER met2 ;
RECT -0.185 -0.185 0.185 0.185 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR_C
VIA M3M4_PR
LAYER met3 ;
RECT -0.19 -0.16 0.19 0.16 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR
VIA M3M4_PR_R
LAYER met3 ;
RECT -0.16 -0.19 0.16 0.19 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR_R
VIA M3M4_PR_M
LAYER met3 ;
RECT -0.19 -0.16 0.19 0.16 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR_M
VIA M3M4_PR_MR
LAYER met3 ;
RECT -0.16 -0.19 0.16 0.19 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR_MR
VIA M3M4_PR_C
LAYER met3 ;
RECT -0.19 -0.19 0.19 0.19 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR_C
VIA M4M5_PR
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR
VIA M4M5_PR_R
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR_R
VIA M4M5_PR_M
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR_M
VIA M4M5_PR_MR
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR_MR
VIA M4M5_PR_C
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR_C
SITE unit
CLASS CORE ;
SYMMETRY Y ;
SIZE 0.46 BY 2.72 ;
END unit
SITE unithddbl
CLASS CORE ;
SIZE 0.46 BY 5.44 ;
END unithddbl
END LIBRARY

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FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.lvs.v Normal file
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FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef (Stored with Git LFS) Normal file
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FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.pt.v Normal file
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FPGA1212_RESET_HD_SKY_PNR/fpga_top/fpga_top_icv_in_design.top_only.pt.v Normal file
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