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[Script] Add design variables to task configuration files

This commit is contained in:
tangxifan 2021-04-01 20:29:30 -06:00
parent 54df2a4f97
commit 7e4595068a
4 changed files with 10 additions and 1 deletions
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1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf
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@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf
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@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga

1
SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf
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@ -14,6 +14,7 @@ spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 1*60 timeout_each_job = 1*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga

8
SNPS_PT/SCRIPT/report_timing_clb.tcl
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@ -51,7 +51,13 @@ link_design ${DESIGN_NAME}
######################################### #########################################
# Setup constraints to break combinational loops # Setup constraints to break combinational loops
set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q if {${DEVICE_NAME} eq "SOFA_HD"} {
set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q
} else {
# QLSOFA and SOFA CHD use a LUT with carry logic, the memory is deeper in hierarchy
# Also QLSOFA and SOFA CHD use a different FF cell as configuration memory
set_disable_timing */*/*/*/*/*mem/sky*_fd_sc_hd__dfrtp_*_*_/Q
}
# #
########################################## ##########################################
## Setup constraints for clocks ## Setup constraints for clocks