From 7e4595068a382f98f31100529233bfb2b426dd12 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 1 Apr 2021 20:29:30 -0600 Subject: [PATCH] [Script] Add design variables to task configuration files --- .../generate_fabric/config/task_template.conf | 1 + .../generate_sdc/config/task_template.conf | 1 + .../generate_testbench/config/task_template.conf | 1 + SNPS_PT/SCRIPT/report_timing_clb.tcl | 8 +++++++- 4 files changed, 10 insertions(+), 1 deletion(-) diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf index 222aee6..1a8d96d 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_fabric/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf index 24bc072..9f8fc0d 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_sdc/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf index 8ffa663..9ace75d 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_caravel_cc_fdhd_12x12/generate_testbench/config/task_template.conf @@ -14,6 +14,7 @@ spice_output=false verilog_output=true timeout_each_job = 1*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml [OpenFPGA_SHELL] openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga diff --git a/SNPS_PT/SCRIPT/report_timing_clb.tcl b/SNPS_PT/SCRIPT/report_timing_clb.tcl index 502a9bb..91a7314 100644 --- a/SNPS_PT/SCRIPT/report_timing_clb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_clb.tcl @@ -51,7 +51,13 @@ link_design ${DESIGN_NAME} ######################################### # Setup constraints to break combinational loops -set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q +if {${DEVICE_NAME} eq "SOFA_HD"} { + set_disable_timing */*/*/mem*/sky*_fd_sc_hd__dfxtp_*_*_/Q +} else { + # QLSOFA and SOFA CHD use a LUT with carry logic, the memory is deeper in hierarchy + # Also QLSOFA and SOFA CHD use a different FF cell as configuration memory + set_disable_timing */*/*/*/*/*mem/sky*_fd_sc_hd__dfrtp_*_*_/Q +} # ########################################## ## Setup constraints for clocks