[Testbench] Restore post-Pnr testbenches for CHD version

2020-12-14 13:17:37 -07:00 · 2020-12-14 13:17:37 -07:00 · 7c0dc4c871
parent 62924d5464
commit 7c0dc4c871
16 changed files with 646 additions and 48 deletions
--- a/TESTBENCH/common/post_pnr_fpga_cells.v
+++ b/TESTBENCH/common/post_pnr_fpga_cells.v
--- a/TESTBENCH/digital_io_hd_test/digital_io_hd_test.v
+++ b/TESTBENCH/digital_io_hd_test/digital_io_hd_test.v
--- a/TESTBENCH/digital_io_hd_test/digital_io_hd_test_include_netlists.v
+++ b/TESTBENCH/digital_io_hd_test/digital_io_hd_test_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v
--- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v
+++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v