diff --git a/TESTBENCH/common/post_pnr_fpga_cells.v b/TESTBENCH/common/post_pnr_fpga_cells.v index 8b2b063..1b18184 100644 --- a/TESTBENCH/common/post_pnr_fpga_cells.v +++ b/TESTBENCH/common/post_pnr_fpga_cells.v @@ -1,3 +1,58 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:13373f025cd88fee0174c4e7a6121fafd658ac735c112267e55f989f60c882f3 -size 8407 +// Include Skywater cell netlists that are used in post PnRed FPGA netlists +// Cells already used pre-PnR +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v" + +// Cells added due to their use in PnR +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_0.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/conb/sky130_fd_sc_hd__conb_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_6.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_6.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_12.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufinv/sky130_fd_sc_hd__bufinv_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinvlp/sky130_fd_sc_hd__clkinvlp_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_12.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_16.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/bufbuf/sky130_fd_sc_hd__bufbuf_8.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2/sky130_fd_sc_hd__nor2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nor2b/sky130_fd_sc_hd__nor2b_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/and2/sky130_fd_sc_hd__and2_0.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/nand2b/sky130_fd_sc_hd__nand2b_1.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/ebufn/sky130_fd_sc_hd__ebufn_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/or2b/sky130_fd_sc_hd__or2b_4.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_2.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_4.v" diff --git a/TESTBENCH/digital_io_hd_test/digital_io_hd_test.v b/TESTBENCH/digital_io_hd_test/digital_io_hd_test.v index 088ade4..931a37b 100644 --- a/TESTBENCH/digital_io_hd_test/digital_io_hd_test.v +++ b/TESTBENCH/digital_io_hd_test/digital_io_hd_test.v @@ -1,3 +1,182 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:772a5684e323a0acb7fce40d406a2e38ccec6ff03b7037fcd28ca3080b80079b -size 5328 +//------------------------------------------- +// Verilog Testbench for Verifying a digital I/O cell +// Description: This test is applicable to the embedded I/O cell +// used in FPGA fabric. This is a self-testing testbench that +// checks the functionality of +// - The I/O isolation signal, which force the I/O in input mode +// - The input mode, +// - where input from SOC can be propagated to FPGA, when enabled +// - where FPGA input holds high-impedence state ('Z'), when disabled +// - The output mode, +// - where output from FPGA can be propagated to SOC, when enabled +// - where SOC output holds high-impedence state ('Z'), when disabled +// +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +`define CLOCK_PERIOD 5 +`define NUM_TEST_CLOCK_CYCLES 10 + +module digital_io_hd_test; +// Local clock to +// - synchronize stimulus generation +// - trigger checkout point +reg [0:0] clock; + +// Local wires for Design Under Test (DUT) +reg [0:0] IO_ISOL_N; +reg [0:0] FPGA_DIR; +reg [0:0] SOC_IN; +reg [0:0] FPGA_OUT; +wire [0:0] SOC_DIR; +wire [0:0] FPGA_IN; +wire [0:0] SOC_OUT; + +// ----- Counters for error checking ----- +integer num_clock_cycles = 0; +integer num_errors = 0; +integer num_checked_points = 0; + +// Clock pulse generation +initial + begin + clock[0] = 1'b0; + end +always + begin + #`CLOCK_PERIOD clock[0] = ~clock[0]; + end + +// IO_ISOL_N stimuli: +// - enabled for two clock cycles +// - disabled then +initial + begin + IO_ISOL_N[0] = 1'b0; + #(`CLOCK_PERIOD*4) IO_ISOL_N[0] = 1'b1; + end + +// FPGA_DIR stimuli: swing between 0 and 1 +// - Test if DIR works when IO_ISOL_N is enabled +// - Test if DIR works when IO_ISOL_N is disabled +initial + begin + FPGA_DIR[0] = 1'b0; + #(`CLOCK_PERIOD) FPGA_DIR[0] = 1'b1; + forever #(`CLOCK_PERIOD*4) FPGA_DIR[0] = ~FPGA_DIR[0]; + end + +// SOC_IN stimuli: swing in the frequency of double clock period +initial + begin + SOC_IN[0] = 1'b0; + end +always + begin + #(`CLOCK_PERIOD*2) SOC_IN[0] = ~SOC_IN[0]; + end + + +// FPGA_OUTPUT stimuli: swing in the frequency of double clock period +initial + begin + FPGA_OUT[0] = 1'b0; + end +always + begin + #(`CLOCK_PERIOD*2) FPGA_OUT[0] = ~FPGA_OUT[0]; + end + +// Instanciate the digital I/O cell + EMBEDDED_IO_HD IO_DUT ( + .IO_ISOL_N(IO_ISOL_N), + .FPGA_DIR(FPGA_DIR), + .FPGA_IN(FPGA_IN), + .FPGA_OUT(FPGA_OUT), + .SOC_DIR(SOC_DIR), + .SOC_IN(SOC_IN), + .SOC_OUT(SOC_OUT) + ); + +// Count number of clock cycles + always @(posedge clock[0]) begin + num_clock_cycles = num_clock_cycles + 1; + end + +// Check expected values at SOC_DIR port + always @(posedge clock[0]) begin + // SOC DIR should stay at logic '1' when IO_ISOL_N is enabled + if (1'b0 == IO_ISOL_N) begin + if (1'b1 !== SOC_DIR) begin + $display("Error: SOC_DIR = %b (expect =%b)", SOC_DIR, 1'b1); + num_errors = num_errors + 1; + end + end else if (1'b1 == IO_ISOL_N) begin + if (FPGA_DIR !== SOC_DIR) begin + $display("Error: SOC_DIR = %b (expect =%b)", SOC_DIR, FPGA_DIR); + num_errors = num_errors + 1; + end + end + num_checked_points = num_checked_points + 1; + end + +// Check expected values at FPGA_IN port + always @(posedge clock[0]) begin + // FPGA_IN should be same as SOC_IN when IO_ISOL_N is enabled + if (1'b0 == IO_ISOL_N) begin + if (SOC_IN !== FPGA_IN) begin + $display("Error: FPGA_IN = %b (expect =%b)", FPGA_IN, SOC_IN); + num_errors = num_errors + 1; + end + end else if (1'b1 == IO_ISOL_N) begin + if (1'b1 == FPGA_DIR) begin + if (SOC_IN !== FPGA_IN) begin + $display("Error: FPGA_IN = %b (expect =%b)", FPGA_IN, SOC_IN); + num_errors = num_errors + 1; + end + end else if (1'b0 == FPGA_DIR) begin + if (1'bz !== FPGA_IN) begin + $display("Error: FPGA_IN = %b (expect =%b)", FPGA_IN, 1'bz); + num_errors = num_errors + 1; + end + end + end + num_checked_points = num_checked_points + 1; + end + +// Check expected values at SOC_OUT port + always @(posedge clock[0]) begin + // SOC_OUT should be 'z' when IO_ISOL_N is enabled + if (1'b0 == IO_ISOL_N) begin + if (1'bz !== SOC_OUT) begin + $display("Error: SOC_OUT = %b (expect =%b)", SOC_OUT, 1'bz); + num_errors = num_errors + 1; + end + end else if (1'b1 == IO_ISOL_N) begin + if (1'b1 == FPGA_DIR) begin + if (1'bz !== SOC_OUT) begin + $display("Error: SOC_OUT = %b (expect =%b)", SOC_OUT, 1'bz); + num_errors = num_errors + 1; + end + end else if (1'b0 == FPGA_DIR) begin + if (FPGA_OUT !== SOC_OUT) begin + $display("Error: SOC_OUT = %b (expect =%b)", SOC_OUT, FPGA_OUT); + num_errors = num_errors + 1; + end + end + end + num_checked_points = num_checked_points + 1; + end + + // Finish after a number of clock cycles + always @(posedge clock[0]) begin + if (`NUM_TEST_CLOCK_CYCLES < num_clock_cycles) begin + $display("Simulation finish with %d errors / %d checkpoints", num_errors, num_checked_points); + $finish; + end + end + +endmodule diff --git a/TESTBENCH/digital_io_hd_test/digital_io_hd_test_include_netlists.v b/TESTBENCH/digital_io_hd_test/digital_io_hd_test_include_netlists.v index 962bab8..210a5c5 100644 --- a/TESTBENCH/digital_io_hd_test/digital_io_hd_test_include_netlists.v +++ b/TESTBENCH/digital_io_hd_test/digital_io_hd_test_include_netlists.v @@ -1,3 +1,8 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:19837156754b79fa200291b62ff5efc0e643a2eba639f111a0950aa03522c944 -size 513 +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/digital_io_hd_primitives.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/digital_io_hd.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/digital_io_hd_test/digital_io_hd_test.v" diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v index e27d149..31150f6 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v @@ -1,3 +1,30 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:85f5b1181ea1f96068bf3cf1400a5e91906d5d03e1f24078af2f22cf337d3985 -size 1381 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_latch_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v index ea37b84..9b3764d 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,32 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:7aa52f799ee631d959d1b6c59e8265e9029c8cbe9fe815fd5246080c1250b794 -size 1485 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_latch_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v index 4f2d3fd..f0856fe 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v @@ -1,3 +1,30 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:feb9721724bd09416b7668d84abf841dcc7805e55c70d098a6edb6601c0f98d3 -size 1377 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Sun Nov 22 13:37:06 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_or2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v index 777ac6d..b3d8325 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,32 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:983e4841c7ec003427faacb444ac6f70d44f44d42b63da875e66339182a8c81a -size 1481 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_or2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v index f1189e3..8006095 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v @@ -1,3 +1,30 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:b5787e2a130f304b78e0befa5a84943ef0bfe5d95336d1fe01f516fca63f85a8 -size 1369 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v index b553d71..b54a5c5 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,32 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:79dd997c27286dbc5a868f683eca4392b3f04b358d425f02878a63656bf2ddff -size 1473 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "and2_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v index ac118c1..ec20af6 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v @@ -1,3 +1,29 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:7fc917a8779c191c7e916af5a6341513d7b341b43eee284d0932414c75c08aaf -size 1321 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_BITSTREAM_SIZE 81452 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/ccff_test_post_pnr_v1.1.v" diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v index 7f1732f..fa60846 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,31 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:d6c23fdce319f8b4e5cf60e07d89aaf83b7479fb1076220d13e894e7627d69bd -size 1495 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_BITSTREAM_SIZE 81452 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v" diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v index 1182769..5d171ec 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v @@ -1,3 +1,30 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:1f3a008a9118f5b619a8c0a2f88830fb596db5d0a7d7a4cf8c36f24832e2b216 -size 1375 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "counter_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v index 84f9214..5cb64dc 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v @@ -1,3 +1,30 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:02e6b21df8939982ee211d8ed61ccb7f6ceb31fa903b2c2c0d9c25971062fb1b -size 1385 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Fri Nov 20 15:48:54 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "routing_test_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v index 96eaa84..949e727 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,32 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:37c31aee9713b1ec359dd5636668defb6220ab6cc8885eee2810b6b359b4a0f7 -size 1489 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`ifdef AUTOCHECKED_SIMULATION + `include "routing_test_output_verilog.v" +`endif + +`ifdef AUTOCHECKED_SIMULATION + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_autocheck_top_tb.v" +`endif + diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index 296749a..b5d8b56 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -1,3 +1,29 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:01cf35ae46aa3f5b4b4f4033461c558876b9317832db844d3ffe841439208e58 -size 1320 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_SCANCHAIN_SIZE 2304 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr_v1.1.v" diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v index 2a2fd2a..7dcda77 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v @@ -1,3 +1,31 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:003df834b79a1294510fe7f0a081e9a987557f92878eff24bbb28bfb441b4beb -size 1494 +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Netlist Summary +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Nov 11 16:01:30 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +`define FPGA_IO_SIZE 144 + +// Design parameter for FPGA bitstream sizes +`define FPGA_SCANCHAIN_SIZE 2304 + +// ------ Include simulation defines ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v" + +// ------ Include Skywater cell netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" + +// ------ Include fabric top-level netlists ----- +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" + +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v"