mirror of https://github.com/lnis-uofu/SOFA.git
Delete .github directory
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parent
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commit
78ee4b0f2a
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@ -1,20 +0,0 @@
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#!/bin/bash
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SCAN_SOFA_HD_KEY="FPGA1212_SOFA_HD_PNR"
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SCAN_QLSOFA_HD_KEY="FPGA1212_QLSOFA_HD_PNR"
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SCAN_SOFA_CHD_KEY="FPGA1212_SOFA_CHD_PNR"
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SCAN_QLAP3_KEY="FPGA1212_QLAP3_PNR"
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# TODO: Strip comments while reading using yq
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# TODO: Add SOFA_CHD and QLAP3 for later
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for repo in SOFA_HD ; do
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ScanDir=$(eval "echo \$SCAN_${repo}_KEY")
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action_filename=$(echo "$repo" | awk '{print tolower($0)}')
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repo_name=$(echo "$repo" | sed "s/_/-/")
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echo $ScanDir $action_filename $repo_name
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cat deploy_sofa.yaml | \
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sed -e "s/SOFA_HD/${repo}/" \
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-e "s/SOFA-HD/${repo_name}/" \
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-e "s/FPGA1212_FLAT_HD_SKY_PNR/${ScanDir}/" | \
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yq r - -X > ./workflows/deploy_${action_filename}.yaml
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done
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@ -1,90 +0,0 @@
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name: Caravel-SOFA_HD Deployment
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# = = = Env Variable = = = = =
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# secrets.TEST_REPO_KEY
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# secrets.SOFA_HD_KEY
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# secrets.SOFA_CHD_KEY
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# secrets.QLSOFA_HD_KEY
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# secrets.QLAP3_KEY
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# yq r -X deploy_sofa.yaml > ./workflows/deploy_sofa_hd.yaml
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env:
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SCAN_DIRECTORY: &SCAN_DIRECTORY
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'FPGA1212_FLAT_HD_SKY_PNR/**'
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PROJ_SUFFIX: &PROJ_SUFFIX
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SOFA_HD
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DEST_DIR: &DEST_DIR
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Caravel-SOFA-HD
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DEST_REPO: &DEST_REPO
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lnis-uofu/Caravel-SOFA-HD
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REPO_KEY: &REPO_KEY
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${{ secrets.SOFA_HD_KEY }}
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CARAVEL_COMPARE_COMMIT: &CARAVEL_COMPARE_COMMIT
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f48448d4736bd6d56fed4dbf7f9cc50552d8745d
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on:
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push:
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paths:
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- '.github/**'
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- 'SynRepoConfig/**'
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- '$SCAN_DIRECTORY'
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branches:
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- ganesh_dev
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pull_request:
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types: closed
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branches:
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- master
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jobs:
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linux:
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name: Updating release repository
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runs-on: ubuntu-latest
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steps:
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- name: Checkout SOFA-Chips
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uses: actions/checkout@v2
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with:
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path: SOFA-Chips
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- name: Checkout caravel repo
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uses: actions/checkout@master
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with:
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repository: *DEST_REPO
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path: *DEST_DIR
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- name: Checkout open_mpw_precheck repo
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uses: actions/checkout@master
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with:
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repository: efabless/open_mpw_precheck
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path: open_mpw_precheck
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- name: Perform checks with open_mpw_precheck
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uses: ganeshgore/docker-run-action@49cd3a1
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with:
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image: goreganesh/open_mpw_prechecker
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options: >
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-v ${{github.workspace}}/open_mpw_precheck:/usr/local/bin
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-v ${{github.workspace}}:/usr/local/workspace
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-e DEST_DIR=$DEST_DIR
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-e SCAN_DIRECTORY=$SCAN_DIRECTORY
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-e PRECHECKER_OPTS="--skip_drc"
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--workdir /usr/local/workspace
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run: cd /usr/local/workspace && pwd && ls && bash ./SOFA-Chips/.github/workflows/perform_precheck.sh
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- name: Deploy files
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run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh
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- name: Local log
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if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
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run:
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git status
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# - name: Deploy Changes localbranch
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# uses: peaceiris/actions-gh-pages@v3
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# if: ${{! (github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged') }}
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# with:
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# user_name: "lnis.uofu"
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# user_email: "lnis.uofu@gmail.com"
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# github_token: ${{ secrets.GITHUB_TOKEN }}
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# publish_dir: ./SOFA-Chips/local_checks/Caravel-SOFA_HD
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# publish_branch: master
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# disable_nojekyll: true
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# commit_message: '[Deployment] ${{ github.event.head_commit.message }}'
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@ -1,50 +0,0 @@
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# ##############################################################################
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# TODO: Add verification task after the netlist modification
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################################################################################
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name: Arch XML Regression
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# Run CI on push on each branch
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on:
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push:
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pull_request:
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jobs:
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generate_netlist:
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name: Arch development
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runs-on: ubuntu-18.04
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container: ghcr.io/lnis-uofu/openfpga-master:latest
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strategy:
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fail-fast: false
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matrix:
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config:
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- name: "FPGA1212_QLSOFA_HD"
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- name: "FPGA1212_SOFA_CHD"
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- name: "FPGA1212_SOFA_HD"
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steps:
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- name: Runner workspace path
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run: |
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echo "Cleaning up previous run"
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rm -rf "${{ github.workspace }}"
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mkdir -p "${{ github.workspace }}"
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- name: Checkout OpenFPGA-ArcticPro3 repo
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uses: actions/checkout@v2
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- name: Detect changes
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uses: technote-space/get-diff-action@v4
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with:
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PATTERNS: |
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${{ matrix.config.name }}_PNR/*_task/**
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- name: Running benchmark
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shell: bash
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if: ${{ env.GIT_DIFF || (github.event_name == 'pull_request' && github.ref == 'refs/heads/master') || (github.ref == 'refs/heads/master') }}
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run: |
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${PYTHON_EXEC} -m pip install -r requirements.txt
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cat ${{ matrix.config.name }}_PNR/${{ matrix.config.name }}_task/config/task_simulation.conf
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cd ${{ matrix.config.name }}_PNR && make clean runOpenFPGA
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- name: Upload artifact
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uses: actions/upload-artifact@v2
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if: ${{ failure() }}
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with:
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name: failed_${{matrix.config.name}}_regression_log
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retention-days: 1
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path: "${{ matrix.config.name }}_PNR/*_task/latest/*.log"
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@ -1,53 +0,0 @@
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# Install all the dependency for OpenFPGA in Ubuntu-18.04
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sudo apt-get update
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sudo apt-get install autoconf
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sudo apt-get install automake
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sudo apt-get install bash
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sudo apt-get install bison
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sudo apt-get install build-essential
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sudo apt-get install cmake
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sudo apt-get install ccache
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sudo apt-get install ctags
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sudo apt-get install curl
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sudo apt-get install doxygen
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sudo apt-get install flex
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sudo apt-get install fontconfig
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sudo apt-get install gdb
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sudo apt-get install git
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sudo apt-get install gperf
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sudo apt-get install iverilog
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sudo apt-get install libcairo2-dev
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sudo apt-get install libevent-dev
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sudo apt-get install libfontconfig1-dev
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sudo apt-get install liblist-moreutils-perl
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sudo apt-get install libncurses5-dev
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sudo apt-get install libx11-dev
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sudo apt-get install libxft-dev
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sudo apt-get install libxml++2.6-dev
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sudo apt-get install perl
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sudo apt-get install python
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sudo apt-get install python3-setuptools
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sudo apt-get install python-lxml
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sudo apt-get install tcllib
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sudo apt-get install tcl8.6-dev
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sudo apt-get install texinfo
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sudo apt-get install time
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sudo apt-get install valgrind
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sudo apt-get install zip
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sudo apt-get install qt5-default
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sudo apt-get install clang-format-7
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# Add all the supported compilers
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sudo apt-get install g++-5
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sudo apt-get install gcc-5
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sudo apt-get install g++-6
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sudo apt-get install gcc-6
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sudo apt-get install g++-7
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sudo apt-get install gcc-7
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sudo apt-get install g++-8
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sudo apt-get install gcc-8
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sudo apt-get install g++-9
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sudo apt-get install gcc-9
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sudo apt-get install clang-6.0
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sudo apt-get install clang-8
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# Python dependencies
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python3 -m pip install -r /home/runner/work/SOFA/SOFA/OpenFPGA/requirements.txt
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@ -1,90 +0,0 @@
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#!/bin/bash
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# Working directory in github workspace
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# Original repo is places ../SOFA-Chips
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# for conditional file copy use PROJ_SUFFIX (example SOFA_HD)
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|
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cd ./${DEST_DIR}
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echo "[Info] Running in directory ${PWD}"
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cp ../SOFA-Chips/${SCAN_DIRECTORY}/fpga_top_icv_in_design.gds.gz ./gds/
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if test -f "./gds/fpga_top_icv_in_design.gds.gz.sha1"; then
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sha1sum --status -c ./gds/fpga_top_icv_in_design.gds.gz.sha1
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status=$?
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[ $status -eq 0 ] && echo "SHA1 matched GDS is already merged ... skipping drc" && exit
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fi
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fpga_top_sha1=$(sha1sum ./gds/fpga_top_icv_in_design.gds.gz)
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make uncompress
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echo "[Info] All files are uncompressed"
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# = = = = = = = = = = = = Modify Merge Scripts = = = = = = = = = = = = = = = =
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AddLine="use fpga_top fpga_top_uut\n"\
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"transform 1 0 0 0 1 0\n"\
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"box 0 0 2500 3000"
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sed -i "s/<< properties >>/${AddLine}\n<< properties >>/" ./mag/user_project_wrapper_empty.mag
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echo "[Info] Updated user_project_wrapper_empty"
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# = = = Running magic to merge fpga_top with user_project_wrapper = = = = = = =
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[ ! -d "/usr/local/workspace/${DEST_DIR}/checks" ] && mkdir /usr/local/workspace/${DEST_DIR}/checks
|
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MAGTYPE=mag \
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magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/current/sky130A.magicrc \
|
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-noconsole -dnull \
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../SOFA-Chips/SCRIPT/merge_fpga_top.tcl </dev/null > \
|
||||
/usr/local/workspace/${DEST_DIR}/checks/magic_merge_user_project_wrapper.log
|
||||
|
||||
git checkout HEAD ./mag/user_project_wrapper_empty.mag
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echo "[Info] merge fpga-top"
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|
||||
# = = = = = = = = = = Build Caravel with Klayout = = = = = = = = = = = = = = =
|
||||
klayout -r ../SOFA-Chips/SCRIPT/merge_caravel_klayout.py -zz > \
|
||||
/usr/local/workspace/${DEST_DIR}/checks/KlayoutMerge.log
|
||||
echo "[Info] Finished shiping chip with Klayout"
|
||||
rm -rf ./gds/fpga_top*
|
||||
rm -rf ./gds/user_project_wrapper_empty.gds
|
||||
rm -rf ./gds/user_proj_example.gds
|
||||
mv ./gds/caravel_merged.gds ./gds/caravel.gds
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||||
|
||||
# = = = = = = = = = Build Caravel with Magic = = = = = = = = = = = = = = = = =
|
||||
# for i in {1..30}; do sleep 1m; echo "Still shipping"; done & # 30 min timeout for merge GDS
|
||||
# make ship
|
||||
# kill %1
|
||||
# echo "[Info] Finished shiping chip with Magic "
|
||||
# rm -f gds/caravel.old.gds
|
||||
|
||||
# = = = = = = = = = = = = = Perform Open MPW Checks = = = = = = = = = = = = = =
|
||||
if [[ "$SKIP_PRECHECK" != 1 ]]; then
|
||||
echo "[Info] Running MPW Prechecker"
|
||||
cd /usr/local/bin
|
||||
python3 open_mpw_prechecker.py \
|
||||
--target_path /usr/local/workspace/${DEST_DIR} \
|
||||
--pdk_root $PDK_ROOT ${PRECHECKER_OPTS}
|
||||
echo "[Info] Finished MPW Prechecker"
|
||||
else
|
||||
make compress
|
||||
echo "[Info] Skipped MPW Prechecker"
|
||||
fi
|
||||
|
||||
# = = = = = = = Convert DRC Errors to RDB = = = = = = = = = = = = = = = = = = =
|
||||
cd /usr/local/workspace/${DEST_DIR}
|
||||
if test -f "./checks/caravel.magic.drc"; then
|
||||
python3 ../SOFA-Chips/SCRIPT/magic_drc_to_rdb.py \
|
||||
--magic_drc_in ./checks/caravel.magic.drc \
|
||||
--rdb_out ./checks/caravel.magic.rdb
|
||||
echo "[Info] Converted errors in RDB format"
|
||||
fi
|
||||
|
||||
# = = = = = = = Clean up repo = = = = = = = = = = = = = = = = = = =
|
||||
rm -rf user_project_wrapper.mag
|
||||
rm -rf gds/caravel.mag
|
||||
rm -rf magic_drc.log
|
||||
git checkout HEAD -- ./mag/user_project_wrapper.mag
|
||||
git checkout HEAD -- ./mag/user_project_wrapper.mag
|
||||
|
||||
echo ${CARAVEL_COMPARE_COMMIT}
|
||||
if [[ 0 -eq $(git cat-file -e $CARAVEL_COMPARE_COMMIT) ]]; then
|
||||
git diff --stat $CARAVEL_COMPARE_COMMIT . > \
|
||||
/usr/local/workspace/${DEST_DIR}/checks/compare_caravel.txt
|
||||
echo "[Info] Create compare_caravel.txt"
|
||||
fi
|
||||
echo $fpga_top_sha1 > ./gds/fpga_top_icv_in_design.gds.gz.sha1
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
###############################################
|
||||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
|
||||
##############################################
|
||||
# Initialize the repository
|
||||
# - Generate final version of architecture files
|
||||
# - Run FPGA tasks to validate netlist generations
|
||||
python3 SCRIPT/repo_setup.py --openfpga_root_path ./OpenFPGA
|
||||
|
||||
# Post processing netlist to use custom cells
|
||||
python3 HDL/common/custom_cell_mux_primitive_generator.py --template_netlist HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/sub_module/mux_primitives.v --output_verilog HDL/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/SRC/sub_module/mux_primitives_hd.v
|
||||
|
||||
##############################################
|
||||
# Generate wrapper HDL codes to bridge Caravel I/Os and FPGA I/Os
|
||||
python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.0.v
|
||||
python3 HDL/common/wrapper_lines_generator.py --template_netlist HDL/common/caravel_fpga_wrapper_hd_template.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --output_verilog HDL/common/caravel_fpga_wrapper_hd_v1.1.v
|
||||
|
||||
##############################################
|
||||
# Generate post-PnR testbenches
|
||||
python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.0.json
|
||||
python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json
|
||||
python3 TESTBENCH/common/generate_post_pnr_testbenches.py --pre_pnr_testbench_dir_name ./TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc --pin_assignment_file ./HDL/common/caravel_wrapper_pin_assignment_v1.1.json
|
||||
|
||||
# Generate wrapper testbenches from template tesbenches for configuration chain tests
|
||||
python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/ccff_test_post_pnr_v1.0.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --wrapper_testbench TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v
|
||||
python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/ccff_test_post_pnr_v1.1.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --wrapper_testbench TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper.v
|
||||
|
||||
# Generate wrapper testbenches from template tesbenches for scan chain tests
|
||||
python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/scff_test_post_pnr_v1.0.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.0.json --wrapper_testbench TESTBENCH/k4_N8_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v
|
||||
python3 TESTBENCH/common/post_pnr_wrapper_testbench_converter.py --post_pnr_testbench TESTBENCH/common/scff_test_post_pnr_v1.1.v --pin_assignment_file HDL/common/caravel_wrapper_pin_assignment_v1.1.json --wrapper_testbench TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper.v
|
||||
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
#!/bin/bash
|
||||
# This script runs after the prechecks and before the deployment
|
||||
# In the host enviroment (All the GITHUB variables are available)
|
||||
|
||||
# Working directory in github workspace
|
||||
# Original repo is places SOFA-Chips
|
||||
# for conditional file copy use PROJ_SUFFIX (example SOFA_HD)
|
||||
COPY_FILE="./SOFA-Chips/SynRepoConfig/sync_files_${PROJ_SUFFIX,,}.csv"
|
||||
echo "[Info] Using file for rsync $COPY_FILE"
|
||||
tail -n +2 $COPY_FILE | while IFS=, read -r srcLoc dstLoc; do
|
||||
srcLoc=$(echo $(eval "echo $srcLoc"))
|
||||
dstLoc=$(echo $(eval "echo $dstLoc"))
|
||||
echo "Copying ./SOFA-Chips/$srcLoc --> ${DEST_DIR}/$dstLoc"
|
||||
rsync -ap ./SOFA-Chips/$srcLoc ${DEST_DIR}/$dstLoc
|
||||
done
|
||||
|
||||
cd ${DEST_DIR}
|
||||
|
||||
[ -s source_commit_hash.txt ] || echo "---- Start ----" > source_commit_hash.txt
|
||||
|
||||
sed -i "1i GITHUB_SHA ${GITHUB_SHA:--}" source_commit_hash.txt
|
||||
sed -i "1i Date $(date)" source_commit_hash.txt
|
||||
sed -i '1i = = = = = = = = = = = = = = = =' source_commit_hash.txt
|
||||
|
||||
# Clean up file from repo
|
||||
git checkout master qflow
|
||||
rm -rf .travis*
|
||||
rm -f .travis.yml
|
||||
find . -xtype l -delete
|
||||
Loading…
Reference in New Issue