mirror of https://github.com/lnis-uofu/SOFA.git
[Script] Update report timing script
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parent
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commit
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#
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#
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##################################
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##################################
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# Define environment variables
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# Define environment variables
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#
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set DEVICE_NAME "SOFA_HD"
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#set DEVICE_NAME "QLSOFA_HD"
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#set DEVICE_NAME "SOFA_CHD"
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
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if {"SOFA_HD" == ${DEVICE_NAME}} {
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set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
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set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
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} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
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set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
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set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
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#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
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#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
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#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
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} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
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set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
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#set DEVICE_NAME "SOFA_HD"
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
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set DEVICE_NAME "QLSOFA_HD"
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}
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#set DEVICE_NAME "SOFA_CHD"
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set TIMING_REPORT_HOME "../TIMING_REPORTS/";
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set TIMING_REPORT_HOME "../TIMING_REPORTS/";
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@ -23,7 +23,6 @@ if {"SOFA_HD" == ${DEVICE_NAME}} {
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
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}
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}
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set TIMING_REPORT_HOME "../TIMING_REPORTS/";
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set TIMING_REPORT_HOME "../TIMING_REPORTS/";
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# Enable preprocessing in Verilog parser
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# Enable preprocessing in Verilog parser
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@ -5,19 +5,24 @@
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##################################
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##################################
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# Define environment variables
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# Define environment variables
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#
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set DEVICE_NAME "SOFA_HD"
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#set DEVICE_NAME "QLSOFA_HD"
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#set DEVICE_NAME "SOFA_CHD"
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
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if {"SOFA_HD" == ${DEVICE_NAME}} {
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set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
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set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
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} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
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set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
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set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
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#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
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#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
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#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
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} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
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set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
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}
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#set DEVICE_NAME "SOFA_HD"
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set DEVICE_NAME "QLSOFA_HD"
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#set DEVICE_NAME "SOFA_CHD"
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set TIMING_REPORT_HOME "../TIMING_REPORTS/";
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set TIMING_REPORT_HOME "../TIMING_REPORTS/";
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@ -5,19 +5,23 @@
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##################################
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##################################
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# Define environment variables
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# Define environment variables
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set DEVICE_NAME "SOFA_HD"
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#set DEVICE_NAME "QLSOFA_HD"
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#set DEVICE_NAME "SOFA_CHD"
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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set SKYWATER_PDK_HOME "../../PDK/skywater-pdk";
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#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
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if {"SOFA_HD" == ${DEVICE_NAME}} {
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set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top";
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set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
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} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} {
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set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
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set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top";
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#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
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#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc";
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc";
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#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
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} elseif {"SOFA_CHD" == ${DEVICE_NAME}} {
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set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top";
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#set DEVICE_NAME "SOFA_HD"
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set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc";
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set DEVICE_NAME "QLSOFA_HD"
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}
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#set DEVICE_NAME "SOFA_CHD"
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set TIMING_REPORT_HOME "../TIMING_REPORTS/";
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set TIMING_REPORT_HOME "../TIMING_REPORTS/";
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# Enable preprocessing in Verilog parser
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# Enable preprocessing in Verilog parser
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