From 77f340cb2f3ddf6e7fed8c40cac30ed0739d4945 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 3 Apr 2021 14:38:01 -0600 Subject: [PATCH] [Script] Update report timing script --- SNPS_PT/SCRIPT/report_timing_cb.tcl | 26 +++++++++++++++----------- SNPS_PT/SCRIPT/report_timing_clb.tcl | 1 - SNPS_PT/SCRIPT/report_timing_io.tcl | 25 +++++++++++++++---------- SNPS_PT/SCRIPT/report_timing_sb.tcl | 26 +++++++++++++++----------- 4 files changed, 45 insertions(+), 33 deletions(-) diff --git a/SNPS_PT/SCRIPT/report_timing_cb.tcl b/SNPS_PT/SCRIPT/report_timing_cb.tcl index fd5fb73..ea32e88 100644 --- a/SNPS_PT/SCRIPT/report_timing_cb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_cb.tcl @@ -5,19 +5,23 @@ # ################################## # Define environment variables +# +set DEVICE_NAME "SOFA_HD" +#set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; -set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; - -#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; -set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; -#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; - -#set DEVICE_NAME "SOFA_HD" -set DEVICE_NAME "QLSOFA_HD" -#set DEVICE_NAME "SOFA_CHD" +if {"SOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"SOFA_CHD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; +} set TIMING_REPORT_HOME "../TIMING_REPORTS/"; diff --git a/SNPS_PT/SCRIPT/report_timing_clb.tcl b/SNPS_PT/SCRIPT/report_timing_clb.tcl index 28aecd3..f983c50 100644 --- a/SNPS_PT/SCRIPT/report_timing_clb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_clb.tcl @@ -23,7 +23,6 @@ if {"SOFA_HD" == ${DEVICE_NAME}} { set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; } - set TIMING_REPORT_HOME "../TIMING_REPORTS/"; # Enable preprocessing in Verilog parser diff --git a/SNPS_PT/SCRIPT/report_timing_io.tcl b/SNPS_PT/SCRIPT/report_timing_io.tcl index 5714dfc..095a3a8 100644 --- a/SNPS_PT/SCRIPT/report_timing_io.tcl +++ b/SNPS_PT/SCRIPT/report_timing_io.tcl @@ -5,19 +5,24 @@ ################################## # Define environment variables +# +set DEVICE_NAME "SOFA_HD" +#set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; -set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; +if {"SOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"SOFA_CHD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; +} -#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; -set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; -#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; - -#set DEVICE_NAME "SOFA_HD" -set DEVICE_NAME "QLSOFA_HD" -#set DEVICE_NAME "SOFA_CHD" set TIMING_REPORT_HOME "../TIMING_REPORTS/"; diff --git a/SNPS_PT/SCRIPT/report_timing_sb.tcl b/SNPS_PT/SCRIPT/report_timing_sb.tcl index 9e426b7..72a8c72 100644 --- a/SNPS_PT/SCRIPT/report_timing_sb.tcl +++ b/SNPS_PT/SCRIPT/report_timing_sb.tcl @@ -5,19 +5,23 @@ ################################## # Define environment variables + +set DEVICE_NAME "SOFA_HD" +#set DEVICE_NAME "QLSOFA_HD" +#set DEVICE_NAME "SOFA_CHD" + set SKYWATER_PDK_HOME "../../PDK/skywater-pdk"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; -set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; -#set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; - -#set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; -set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; -#set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; - -#set DEVICE_NAME "SOFA_HD" -set DEVICE_NAME "QLSOFA_HD" -#set DEVICE_NAME "SOFA_CHD" +if {"SOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"QLSOFA_HD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_QLSOFA_HD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc"; +} elseif {"SOFA_CHD" == ${DEVICE_NAME}} { + set FPGA_NETLIST_HOME "../../FPGA1212_SOFA_CHD_PNR/fpga_top"; + set SDC_HOME "../../SDC/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc"; +} set TIMING_REPORT_HOME "../TIMING_REPORTS/"; # Enable preprocessing in Verilog parser